active low reset

[googler]

Most of the verilog RTL codes that I have seen use reset signal as
active low. For example, consider the sequential 'always' block below.

always @(posedge CLK or negedge RSTn)
begin
if (~RSTn)
xyz <= 1'b0;
else
xyz <= next_xyz;
end

Although I do the same myself, I don't know if there is any specific
reason behind using reset as active low (as compared to active high)?
Is it just a matter of convention or is there any real advantage?
Thanks.

 

[General Schvantzkoph]

On Tue, 08 Jun 2010 10:16:26 -0700, googler wrote:

Most of the verilog RTL codes that I have seen use reset signal as
active low. For example, consider the sequential 'always' block below.

always @(posedge CLK or negedge RSTn) begin
if (~RSTn)
xyz <= 1'b0;
else
xyz <= next_xyz;
end

Although I do the same myself, I don't know if there is any specific
reason behind using reset as active low (as compared to active high)? Is
it just a matter of convention or is there any real advantage? Thanks.

It's a hold over from TTL design, the voltages thresholds for TTL drivers
are asymmetric, they are also commonly terminated with pullup resistors.
A low reset is less susceptible to noise then a high reset in a TTL
system. Inside of a chip these conditions don't apply so you can use
either although the default reset levels in FPGAs are high true not low
true. I generally use high true signals inside of FPGAs and ASICs but
stick to the low true convention for external control signals.

 

[David Rogoff]

On 2010-06-08 10:58:31 -0700, General Schvantzkoph said:

On Tue, 08 Jun 2010 10:16:26 -0700, googler wrote:

Most of the verilog RTL codes that I have seen use reset signal as
active low. For example, consider the sequential 'always' block below.

always @(posedge CLK or negedge RSTn) begin
if (~RSTn)
xyz <= 1'b0;
else
xyz <= next_xyz;
end

Although I do the same myself, I don't know if there is any specific
reason behind using reset as active low (as compared to active high)? Is
it just a matter of convention or is there any real advantage? Thanks.

It's a hold over from TTL design, the voltages thresholds for TTL drivers
are asymmetric, they are also commonly terminated with pullup resistors.
A low reset is less susceptible to noise then a high reset in a TTL
system. Inside of a chip these conditions don't apply so you can use
either although the default reset levels in FPGAs are high true not low
true. I generally use high true signals inside of FPGAs and ASICs but
stick to the low true convention for external control signals.

The resets of the actual flip-flops in ASIC are still usually
active-low. However, it doesn't really matter since resets will be
distributed via a tree of inverters, so you'd just need an odd number
of levels in the tree.

 

[gabor]

On Jun 8, 1:16 pm, googler <pinaki_...@yahoo.com> wrote:

Most of the verilog RTL codes that I have seen use reset signal as
active low. For example, consider the sequential 'always' block below.

always @(posedge CLK or negedge RSTn)
begin
    if (~RSTn)
       xyz <= 1'b0;
    else
       xyz <= next_xyz;
end

Although I do the same myself, I don't know if there is any specific
reason behind using reset as active low (as compared to active high)?
Is it just a matter of convention or is there any real advantage?
Thanks.

Generally there's no good reason inside a chip, since you can have
reset generators that start up high or low at power-on. Board-level
resets tend to be active low because it's easier to hold a signal
low until the power supplies are stable. It also goes back to
early bipolar logic that used NAND gates to form flip-flops and
therefore it was easier to make control inputs active low.

Inside the chip I tend to make all of my signals active high to
reduce mistakes made when trying to DeMorgan logic equations
in my head. I suppose it's a matter of preference, though.

Regards,
Gabor

 

On Jun 8, 1:16 pm, googler <pinaki_...@yahoo.com> wrote:

Although I do the same myself, I don't know if there is any specific
reason behind using reset as active low (as compared to active high)?
Is it just a matter of convention or is there any real advantage?

My understanding is that the inputs of the early TTL logic families
went high if unconnected. By making certain control inputs active
low, you could simply leave them unconnected if you weren't using
them. In the later families, this was no longer reliable and the
practice became discouraged. However, the newer chips still had to be
functionally compatible with the older ones, so the inputs remained
active low.

In contrast, ECL chip inputs were guaranteed to go low if
unconnected. As you would expect, most of their control inputs were
active high.

 

[General Schvantzkoph]

On Tue, 08 Jun 2010 23:31:01 +0000, glen herrmannsfeldt wrote:

sharp@cadence.com wrote:
(snip)

My understanding is that the inputs of the early TTL logic families
went high if unconnected. By making certain control inputs active low,
you could simply leave them unconnected if you weren't using them. In
the later families, this was no longer reliable and the practice became
discouraged. However, the newer chips still had to be functionally
compatible with the older ones, so the inputs remained active low.

As I understood it, you shouldn't rely on inputs floating high, but they
usually did.

I though the reason was related to the fact that TTL outputs sink more
current than they source.

Also, in the cases where you wanted to use multiple open-collector
outputs with a pull-up it would work as a wire-OR with active low.

-- glen

TTL could sink 20 ma and source about 2 ma, some drivers were able to
sink 24 ma. That's why terminators were generally pullup resistors. A
line with a pullup resistor instead of a parallel terminator would be
pulled up to 5V which is safely above the high threshold which was around
2.4V as I remember.

 

[glen herrmannsfeldt]

sharp@cadence.com wrote:
(snip)

My understanding is that the inputs of the early TTL logic families
went high if unconnected. By making certain control inputs active
low, you could simply leave them unconnected if you weren't using
them. In the later families, this was no longer reliable and the
practice became discouraged. However, the newer chips still had to be
functionally compatible with the older ones, so the inputs remained
active low.

As I understood it, you shouldn't rely on inputs floating
high, but they usually did.

I though the reason was related to the fact that TTL outputs
sink more current than they source.

Also, in the cases where you wanted to use multiple open-collector
outputs with a pull-up it would work as a wire-OR with active low.

-- glen

 

[d_s_klein]

On Jun 8, 10:16 am, googler <pinaki_...@yahoo.com> wrote:

Most of the verilog RTL codes that I have seen use reset signal as
active low. For example, consider the sequential 'always' block below.

always @(posedge CLK or negedge RSTn)
begin
    if (~RSTn)
       xyz <= 1'b0;
    else
       xyz <= next_xyz;
end

Although I do the same myself, I don't know if there is any specific
reason behind using reset as active low (as compared to active high)?
Is it just a matter of convention or is there any real advantage?
Thanks.

As others have pointed out, if you have enough gray hair you can
remember when it made a difference.

Rule #1 is to make all resets in a design the same polarity.
Rule #2 is to check the global reset for your FPGA and follow that
(ASIC guys get to ignore rule 2)
Rule #3 is to follow whatever support logic you are using (FPGA guys
get to fight rule #3).

RK

 

[gabor]

On Jun 9, 2:27 pm, d_s_klein <d_s_kl...@yahoo.com> wrote:

On Jun 8, 10:16 am, googler <pinaki_...@yahoo.com> wrote:

Most of the verilog RTL codes that I have seen use reset signal as
active low. For example, consider the sequential 'always' block below.

always @(posedge CLK or negedge RSTn)
begin
    if (~RSTn)
       xyz <= 1'b0;
    else
       xyz <= next_xyz;
end

Although I do the same myself, I don't know if there is any specific
reason behind using reset as active low (as compared to active high)?
Is it just a matter of convention or is there any real advantage?
Thanks.

As others have pointed out, if you have enough gray hair you can
remember when it made a difference.

Rule #1 is to make all resets in a design the same polarity.
Rule #2 is to check the global reset for your FPGA and follow that
(ASIC guys get to ignore rule 2)
Rule #3 is to follow whatever support logic you are using (FPGA guys
get to fight rule #3).

RK

Anyone who buys or uses IP from different sources also ignores
rule #1.

 

[nemo]

On Jun 8, 9:03 pm, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:

On Tue, 08 Jun 2010 23:31:01 +0000, glen herrmannsfeldt wrote:
sh...@cadence.com wrote:
(snip)

My understanding is that the inputs of the early TTL logic families
went high if unconnected.  By making certain control inputs active low,
you could simply leave them unconnected if you weren't using them.  In
the later families, this was no longer reliable and the practice became
discouraged.  However, the newer chips still had to be functionally
compatible with the older ones, so the inputs remained active low.

As I understood it, you shouldn't rely on inputs floating high, but they
usually did.

I though the reason was related to the fact that TTL outputs sink more
current than they source.

Also, in the cases where you wanted to use multiple open-collector
outputs with a pull-up it would work as a wire-OR with active low.

-- glen

TTL could sink 20 ma and source about 2 ma, some drivers were able to
sink 24 ma. That's why terminators were generally pullup resistors. A
line with a pullup resistor instead of a parallel terminator would be
pulled up to 5V which is safely above the high threshold which was around
2.4V as I remember.

TTL logic families use a multiple emitter NPN transistor on the input
with the base tied high through a resistor. When the inputs are
pulled low the collector pulls low driving the base of the next
stage. If the inputs are not tied high, but rather left open, the
base current pulls the inputs high, but not very hard. Any sort of
noise on the input can turn the input transistor on causing a glitch.
I have seen more than once designs that had this problem. Anyone who
let TTL inputs float was a greenhorn. That's a mistake you don't make
twice.

ECL didn't have this problem because the outputs were open collector
(or open emitter actually) and ALWAYS had a termination resistor
pulling the output to about 2.0 or 2.1 volts, IIRC. Well, I guess
that didn't mean the inputs would be tied, but there were lots of
termination resistors so finding one to tie off an unused input wasn't
a problem.

Rick