Active-HDL/Xilinx Core FIFO Gen Sim Problem

[roleohibachi]

Hi there,
I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I
used Aldec's design flow tools to implement a Coregen FIFO, and am
using a recent, manufacturer-compiled version of XilinxCoreLib.
The project (3 files: my vhdl, the fifo_generator vhdl and the
fifo_gen .edn) compiles just fine, but when I go to simulate in
Waveform Editor, the part responds "dumb" (all outputs and internal
signals floating, no matter the input), and I get the following
warnings:

# ELBREAD: Warning: Library
fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib not found.
# ELBREAD: Warning: Design unit
fifo_generator_v4_3_fifo_generator_v4_3_xst_1 instantiated in
corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in
searched libraries: corefifo_test,
fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib.
# ELBREAD: Warning: Component /fifo1/BU2 :
fifo_generator_v4_3_fifo_generator_v4_3_xst_1 not bound.
# ELBREAD: Warning: Design unit GND instantiated in
corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in
searched libraries: corefifo_test, spartan3a.
# ELBREAD: Warning: Component /fifo1/GND : GND not bound.

I've checked what exists in my XilinxCoreLib, and I've got all the
following:
fifo_generator_v4_3
fifo_generator_v4_3_bhv_as
fifo_generator_v4_3_bhv_preload0
fifo_generator_v4_3_bhv_ss
fifo_generator_v4_3_xst

So I know that the xst source exists, and is compiled into the
library.

Any help would be greatly appreciated!

 

[Benjamin Couillard]

On 30 jan, 12:32, roleohibachi <roleohiba...@gmail.com> wrote:

Hi there,
I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I
used Aldec's design flow tools to implement a Coregen FIFO, and am
using a recent, manufacturer-compiled version of XilinxCoreLib.
The project (3 files: my vhdl, the fifo_generator vhdl and the
fifo_gen .edn) compiles just fine, but when I go to simulate in
Waveform Editor, the part responds "dumb" (all outputs and internal
signals floating, no matter the input), and I get the following
warnings:

# ELBREAD: Warning: Library
fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib not found.
# ELBREAD: Warning: Design unit
fifo_generator_v4_3_fifo_generator_v4_3_xst_1 instantiated in
corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in
searched libraries: corefifo_test,
fifo_generator_v4_3_fifo_generator_v4_3_xst_1_lib.
# ELBREAD: Warning: Component /fifo1/BU2 :
fifo_generator_v4_3_fifo_generator_v4_3_xst_1 not bound.
# ELBREAD: Warning: Design unit GND instantiated in
corefifo_test.fifo_generator_v4_3(fifo_generator_v4_3) not found in
searched libraries: corefifo_test, spartan3a.
# ELBREAD: Warning: Component /fifo1/GND : GND not bound.

I've checked what exists in my XilinxCoreLib, and I've got all the
following:
  fifo_generator_v4_3
  fifo_generator_v4_3_bhv_as
  fifo_generator_v4_3_bhv_preload0
  fifo_generator_v4_3_bhv_ss
  fifo_generator_v4_3_xst

So I know that the xst source exists, and is compiled into the
library.

Any help would be greatly appreciated!

1 - First, you must download the 10.1 libraries for Aldec 8.1, not the
newest verion of the Xilinx libraries since they probably are for
version ISE 13.1. Make sure you do not download libraries for Aldec
8.3 either.

2 - If you go in the library manager in Active-HDL, check the
different Xilinx libraries and you should be able to see what version
of the fifo generator you have. For example, check unisim or
Xilinxcorelib, names similar to that.

3 - There is a global library file somewhere for Aldec, don't remember
where exactly, but if your library is missing in the library manager,
you need to add this library to the global library file.

 

[Michael Seery]

Thanks for your help. Turns out, all the libraries were spot-on, and it didn't make a difference whether it was attached globally or locally.
Called Aldec, took an hour. Made a newbie mistake. Here's the details, for anyone with the same problem later:
I was including the EDIF (.edn) file in the compilation. The EDIF is for skipping synthesis and has nothing to do with compiling. It was automatically generated by the CoreGen Wizard, and I had just assumed it was a dependency for the FIFO. The compiler was allowing it, but in elaboration, it barfed.. All I had to do was exclude the .edn file from compilation, and everything worked.

Thanks again.

 

[MBodnar]

On Jan 31, 10:39 am, Michael Seery <roleohiba...@gmail.com> wrote:

Thanks for your help. Turns out, all the libraries were spot-on, and it didn't make a difference whether it was attached globally or locally.
Called Aldec, took an hour. Made a newbie mistake. Here's the details, for anyone with the same problem later:
I was including the EDIF (.edn) file in the compilation. The EDIF is for skipping synthesis and has nothing to do with compiling. It was automatically generated by the CoreGen Wizard, and I had just assumed it was a dependency for the FIFO. The compiler was allowing it, but in elaboration, it barfed. All I had to do was exclude the .edn file from compilation, and everything worked.

Thanks again.

Hi Michael,

Glad you figured it out! Ultimately, they are different forms of the
same thing, to be used for different purposes. CoreGen generates lots
of fun stuff in addition to the *.vhd or *.ngc.

Careful with your wording, though. There is an immense difference
between "compiling for simulation" and "compiling for synthesis."
Both are "compiling."

And EDIFs can be used in simulation, with proper library support.

Cheers,

MB