R
Rick C
Guest
My code is assigning an incremented unsigned value to an aggregate so the sum and carry can be extracted without duplicating logic or excessive lines of code (VHDL can be verbose we all know). But it seems this one usage makes the Active-HDL simulator complain. I\'m adding an integer 1 to the unsigned counter value after being resized to be 1 bit larger to match the left hand side aggregate. I\'ll post the code below.
It seems the combination of using the left hand aggregate, resized unsigned and the addition/subtraction of an integer is what causes a problem. I would report this to Aldec, but I\'m pretty sure they don\'t have a way to report bugs if you are not a customer with a current maintenance contract.
-- Test synthesis of counters and carry out flags
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- use work.Common.all;
entity VHDL_test is
generic(
CLK_HZ : REAL := 33.554432E6 );
port(
-- Clk : in std_logic := \'1\';
Cnt_En : in std_logic := \'1\';
Test_Out_a : out std_logic;
Carry_Out_a : out std_logic
);
end VHDL_test;
architecture TB_ARCH of VHDL_test is
constant Clock_Half_Period : time := 500 ms / CLK_HZ; -- 14901 ps;
constant Cntr_Width : positive := 8;
constant Cntr_Modulus : positive := 2**Cntr_Width;
constant One_slv : unsigned(Cntr_Width downto 0) := \"000000001\";
signal Clk : std_logic := \'1\';
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => \'0\');
begin
Clk_gen: Clk <= not Clk after Clock_Half_Period; -- comment out for synth
-- (Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a\'length + 1) - One_slv;
(Carry_Out_a, nxt_cnt_a) <= (\"0\" & Count_a) - 1;
test_ag: process (Clk) is
begin
if rising_edge(Clk) then
Test_Out_a <= Carry_Out_a;
if (Cnt_En OR not Carry_Out_a) then
Count_a <= nxt_cnt_a;
end if;
end if;
end process test_ag;
end TB_ARCH; -- VHDL_test
--
Rick C.
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It seems the combination of using the left hand aggregate, resized unsigned and the addition/subtraction of an integer is what causes a problem. I would report this to Aldec, but I\'m pretty sure they don\'t have a way to report bugs if you are not a customer with a current maintenance contract.
-- Test synthesis of counters and carry out flags
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- use work.Common.all;
entity VHDL_test is
generic(
CLK_HZ : REAL := 33.554432E6 );
port(
-- Clk : in std_logic := \'1\';
Cnt_En : in std_logic := \'1\';
Test_Out_a : out std_logic;
Carry_Out_a : out std_logic
);
end VHDL_test;
architecture TB_ARCH of VHDL_test is
constant Clock_Half_Period : time := 500 ms / CLK_HZ; -- 14901 ps;
constant Cntr_Width : positive := 8;
constant Cntr_Modulus : positive := 2**Cntr_Width;
constant One_slv : unsigned(Cntr_Width downto 0) := \"000000001\";
signal Clk : std_logic := \'1\';
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => \'0\');
begin
Clk_gen: Clk <= not Clk after Clock_Half_Period; -- comment out for synth
-- (Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a\'length + 1) - One_slv;
(Carry_Out_a, nxt_cnt_a) <= (\"0\" & Count_a) - 1;
test_ag: process (Clk) is
begin
if rising_edge(Clk) then
Test_Out_a <= Carry_Out_a;
if (Cnt_En OR not Carry_Out_a) then
Count_a <= nxt_cnt_a;
end if;
end if;
end process test_ag;
end TB_ARCH; -- VHDL_test
--
Rick C.
- Get 1,500 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209