T
talkb
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Has anyone succesfully used Aldec Active HDL 7.3 (web-eval) with a (Verilog)
Smartmodel simulation?
I'm using Xilinx Webpack 9.2i.04 (IP-Update#2), and I separately downloaded
and
installed the Aldec Verilog library-update for 9.2i.04.
In Coregen 9.2i.04 (IPUpdate#2), I created a Verilog Virtex5/LXT50 TEMAC. I
compiled
the core-generated testbench, then added it to my Aldec design-space. I
followed
the directions at
http://support.aldec.com/KnowledgeBase/Article.aspx?aid=000713
I can compile everything successfully, but when i goto initialize
simulation, it fails:
# : SWIFT: Session terminated.
# PLI: SWIFT: Template TEMAC_SWIFT_lmtv not found in SmartModel Library!!!:
$lm_model (0)
# RUNTIME: RUNTIME_0068 $finish called.
# KERNEL: Time: 0 ps, Iteration: 0, Instance:
/testbench/dut/v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/temac_swift_1/I1,
Process: #INTERNAL#0_391.
I've double-checked to make sure Smartmodel-library was installed correctly,
I recompiled the swift_lmtv.dll -- basically I tried everything I could
think of, but
it doesn't work.
I tried a different simulation-design -- RocketIO GTP (from Xilinx
core-generator)
It fails the same way:
# PLI: SWIFT: Template GTP_DUAL_SWIFT_lmtv not found in SmartModel
Library!!!: $lm_model (0
similar failure.
Here's a more complete logfile:
asim -pli "$aldec\BIN\swift.dll" -pli "$aldec\BIN\swift_lmtv.dll" -pli
"C:\Xilinx92i\smartmodel\nt\installed_nt\lib\pcnt.lib\swiftpli.dll" -advdataflow
-L ovi_simprim -L ovi_unisim -L ovi_xilinxcorelib glbl testbench
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0.
# asim: Stack memory: 32MB
# asim: Retval memory: 32MB
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ps.
# ELAB2: Elaboration final pass...
# KERNEL: PLI/VHPI kernel's engine initialization done.
# PLI: Loading library 'C:\Program Files\Aldec\Active-HDL 7.3\bin/systf.dll'
# PLI: Loading library 'C:\Program Files\Aldec\Active-HDL 7.3\BIN\swift.dll'
# PLI: Loading library 'C:\Program Files\Aldec\Active-HDL
7.3\BIN\swift_lmtv.dll'
# ELAB2: Create instances ...
# ELAB2: Create instances complete.
# ELAB2: Elaboration final pass complete - time: 0.1.
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 4394 kB (elbread=2054 elab2=1973
kernel=367 sdf=0)
# : SWIFT: Beginning the session.
# : Copyright (c) 1984-2008 Synopsys Inc. ALL RIGHTS RESERVED
# : You can use the Browser tool to configure the SmartModel
# : Library and access information about SmartModels:
# : $LMC_HOME/bin/sl_browser
# :
# : SmartModel product documentation is available here:
# : $LMC_HOME/doc/smartmodel/manuals/intro.pdf
# : http://www.synopsys.com/products/lm/doc/smartmodel.html
# :
# : SWIFT: Session terminated.
# PLI: SWIFT: Template TEMAC_SWIFT_lmtv not found in SmartModel Library!!!:
$lm_model (0)
# RUNTIME: RUNTIME_0068 $finish called.
# KERNEL: Time: 0 ps, Iteration: 0, Instance:
/testbench/dut/v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/temac_swift_1/I1,
Process: #INTERNAL#0_391.
# KERNEL: ASDB file was created in location
c:\temp\coregen\v5_emac_v1_3\simulation\temac\temac\src\wave.asdb
# 11:47 PM, Monday, January 28, 2008
# Simulation has been initialized
# Selected Top-Level: glbl testbench
Smartmodel simulation?
I'm using Xilinx Webpack 9.2i.04 (IP-Update#2), and I separately downloaded
and
installed the Aldec Verilog library-update for 9.2i.04.
In Coregen 9.2i.04 (IPUpdate#2), I created a Verilog Virtex5/LXT50 TEMAC. I
compiled
the core-generated testbench, then added it to my Aldec design-space. I
followed
the directions at
http://support.aldec.com/KnowledgeBase/Article.aspx?aid=000713
I can compile everything successfully, but when i goto initialize
simulation, it fails:
# : SWIFT: Session terminated.
# PLI: SWIFT: Template TEMAC_SWIFT_lmtv not found in SmartModel Library!!!:
$lm_model (0)
# RUNTIME: RUNTIME_0068 $finish called.
# KERNEL: Time: 0 ps, Iteration: 0, Instance:
/testbench/dut/v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/temac_swift_1/I1,
Process: #INTERNAL#0_391.
I've double-checked to make sure Smartmodel-library was installed correctly,
I recompiled the swift_lmtv.dll -- basically I tried everything I could
think of, but
it doesn't work.
I tried a different simulation-design -- RocketIO GTP (from Xilinx
core-generator)
It fails the same way:
# PLI: SWIFT: Template GTP_DUAL_SWIFT_lmtv not found in SmartModel
Library!!!: $lm_model (0
similar failure.
Here's a more complete logfile:
asim -pli "$aldec\BIN\swift.dll" -pli "$aldec\BIN\swift_lmtv.dll" -pli
"C:\Xilinx92i\smartmodel\nt\installed_nt\lib\pcnt.lib\swiftpli.dll" -advdataflow
-L ovi_simprim -L ovi_unisim -L ovi_xilinxcorelib glbl testbench
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0
# asim: Stack memory: 32MB
# asim: Retval memory: 32MB
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ps.
# ELAB2: Elaboration final pass...
# KERNEL: PLI/VHPI kernel's engine initialization done.
# PLI: Loading library 'C:\Program Files\Aldec\Active-HDL 7.3\bin/systf.dll'
# PLI: Loading library 'C:\Program Files\Aldec\Active-HDL 7.3\BIN\swift.dll'
# PLI: Loading library 'C:\Program Files\Aldec\Active-HDL
7.3\BIN\swift_lmtv.dll'
# ELAB2: Create instances ...
# ELAB2: Create instances complete.
# ELAB2: Elaboration final pass complete - time: 0.1
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 4394 kB (elbread=2054 elab2=1973
kernel=367 sdf=0)
# : SWIFT: Beginning the session.
# : Copyright (c) 1984-2008 Synopsys Inc. ALL RIGHTS RESERVED
# : You can use the Browser tool to configure the SmartModel
# : Library and access information about SmartModels:
# : $LMC_HOME/bin/sl_browser
# :
# : SmartModel product documentation is available here:
# : $LMC_HOME/doc/smartmodel/manuals/intro.pdf
# : http://www.synopsys.com/products/lm/doc/smartmodel.html
# :
# : SWIFT: Session terminated.
# PLI: SWIFT: Template TEMAC_SWIFT_lmtv not found in SmartModel Library!!!:
$lm_model (0)
# RUNTIME: RUNTIME_0068 $finish called.
# KERNEL: Time: 0 ps, Iteration: 0, Instance:
/testbench/dut/v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/temac_swift_1/I1,
Process: #INTERNAL#0_391.
# KERNEL: ASDB file was created in location
c:\temp\coregen\v5_emac_v1_3\simulation\temac\temac\src\wave.asdb
# 11:47 PM, Monday, January 28, 2008
# Simulation has been initialized
# Selected Top-Level: glbl testbench