Actel Designer: how to compile VHDL top & EDIF submodule tog

R

robotron

Guest
Hello,

I need to implement a measurement instrument in FPGA, where direct
placement of several simple blocks (eg. DFFs) must be achieved. So I
created an EDIF netlist, describing one subcircuit, and the rest (top
level entity) coded in VHDL. The target architecture is Actel
ProASIC3E, development suite Libero 9 & Synplify.

The VHDL part has been synthesised using Synplify, producing well-
looking EDIF. Then, I tried to compile (and I hoped then to P&R) the
two .edn files using Actel Designer. However, here comes the failure.
The "inner" subcircuit has not been wired together with the top
entity, compiler returns error about unconnected inputs/outputs and
when I look into structural VHDL output from the compiler, the inner
entity is listed in, but with *empty* implementation. (I tried both
GUI as well as commandline+Tcl Designer invocation, same results.) I
listed the top level entity .edn as the last (ie. the second) in the
list, as mentioned in instructions.

Then, I created another project, entered random dummy VHDL entity with
same i/o signals as the EDIF one mentioned above and synthesised by
Synplify. I have tried the resulting .edn in place of the former one,
same result.

Please, do you have any EDIF example, which is working together with a
VHDL or Verilog together in Actel tools? Or do you know, what am I
doing wrong? Many thanks.


Greetings,
Marek
 
Hello Marek,

There are some challenges in merging EDIF netlists with Designer upon
import. I would let Synplify do the merging for you. Just have your
netlist in VHDL format and add it as an other source file. You can use
the edn2vhdl tool to create the VHDL netlist.

Regards,
Daniel Leu

Inicore Inc.



On Jan 3, 10:14 am, robotron <hefais...@gmail.com> wrote:
Hello,

I need to implement a measurement instrument in FPGA, where direct
placement of several simple blocks (eg. DFFs) must be achieved. So I
created an EDIF netlist, describing one subcircuit, and the rest (top
level entity) coded in VHDL. The target architecture is Actel
ProASIC3E, development suite Libero 9 & Synplify.

The VHDL part has been synthesised using Synplify, producing well-
looking EDIF. Then, I tried to compile (and I hoped then to P&R) the
two .edn files using Actel Designer. However, here comes the failure.
The "inner" subcircuit has not been wired together with the top
entity, compiler returns error about unconnected inputs/outputs and
when I look into structural VHDL output from the compiler, the inner
entity is listed in, but with *empty* implementation. (I tried both
GUI as well as commandline+Tcl Designer invocation, same results.) I
listed the top level entity .edn as the last (ie. the second) in the
list, as mentioned in instructions.

Then, I created another project, entered random dummy VHDL entity with
same i/o signals as the EDIF one mentioned above and synthesised by
Synplify. I have tried the resulting .edn in place of the former one,
same result.

Please, do you have any EDIF example, which is working together with a
VHDL or Verilog together in Actel tools? Or do you know, what am I
doing wrong? Many thanks.

Greetings,
Marek
Click to expand...
 
Hello, Daniel,

There are some challenges in merging EDIF netlists with Designer upon
import. I would let Synplify do the merging for you. Just have your
netlist in VHDL format and add it as an other source file. You can use
the edn2vhdl tool to create the VHDL netlist.
Click to expand...
thank you for your answer. This is the problem: I need to bypass
synthesis step, since I am afraid, that some evil optimization could
damage my design. Even if it would work one, I have no guarantee, that
in next Synplify release it will result in exactly the same output
netlist.

However, I have been told the solution by Actel technical support, so
I am forwarding the reply:
-----
From Sagar.Gosavi@microsemi.com Tue Jan 4 10:51:54 2011
Date: Tue, 4 Jan 2011 15:21:54 +0530
From: "Gosavi, Sagar" <Sagar.Gosavi@microsemi.com>
To: Marek Peca
Subject: RE: Actel Designer: how to compile VHDL top & EDIF submodule
together?:
489394-344304373

Hi Marek,

Thanks for contacting Actel Tech Support.

Can you please send me the design files for this project so that I
can understand the scenario better?

Between, if I understand the situation; are you observing some errors
like:

Error: CMP002: Net: CNT_16[0] is not driven
Error: CMP002: Net: CNT_16[1] is not driven
Error: CMP002: Net: CNT_16[2] is not driven
Error: CMP002: Net: CNT_16[3] is not driven

Also, if you find syn_black_box in your top level edn, kindly replace
it with the instance name of your subcircuit edn.

Note: The library name, cell name and the view name of the lower
level cell/edn has to match in its instantiation in the upper (in
this case, the top level) level

If above solution doesn't help, please send me your Project, so that
I can debug this issue better.

Have a great day ahead!

Thanks and Regards,
Sagar Gosavi
-----

So I have changed the library name to "work" and view name to
"syn_black_box" and now it works as expected, the Designer now
produces reasonably looking composite netlist. The EDIF excerpt looks
like:

(library work
(edifLevel 0)
(technology (numberDefinition))
(cell my_strange_circuit
(cellType GENERIC)
(view syn_black_box (viewType NETLIST)

....etc.


Greetings,
Marek
 
On Jan 3, 7:14 pm, robotron <hefais...@gmail.com> wrote:
Hello,
...
Click to expand...

Time ago I had the same problem with Synplify and VHDL.

My first suggestion is to try with Mentor Precision compiler, recently
distributed with the actel suite.
Never tried but could be the painless solution.

If you want continue to work with vhdl+Symplify, follow the suggestion
from Daniel.
Symplify is able to make magic things also when you mix edif with vhdl/
verilog.

In my case I switched to Verilog+Symplify and everything went fine.
Some more details about this.
If I understood correctly from your post, the verilog version of what
you try to do should be something like the followings.
////// FILE: top.v
`timescale 1 ns/100 ps
module sub_mod_v (CLK,Q,D) /* synthesis syn_black_box */;
output Q;
input CLK;
input D;
endmodule
module top(Q_1, Q_0, CLK, D);
output Q_1;
output Q_0;
input CLK;
input D;
sub_mod_v sub_mod_v_0 (.CLK(CLK), .Q(Q_0), .D(D));
sub_mod_v sub_mod_v_1 (.CLK(CLK), .Q(Q_1), .D(D));
endmodule

////// FILE: sub_mod.v
`timescale 1 ns/100 ps
module sub_mod_v(CLK, Q, D);
input CLK;
output Q;
input D;
DFN1 DFN1_0 (.D(D), .CLK(CLK), .Q(Q));
endmodule

With Symplify,
* compile sub_mod.v after having disabled IO insertion. You get:
"sub_mod.edn"
and separately
* compile top.v . You get: "top.edn"

Then execute Designer and import the two .edn files with "top.edn"
at the end.
You should get a successful designer compiling (just tried).

Last suggestion if you want stay with VHDL (not recommended but it
works).
You can edit the edif TOP file and correct the 'mistake'. It is
related to how Symplify treat VHDL black box. To let you to begin, if
interested, here some tip.
/0/ Look inside top edif file looking for all lines like:
...
(instance sub_mod_0 (viewRef syn_black_box (cellRef sub_mod))
...

and modify them as in the following example
...
(instance sub_mod_0 (viewRef def_arch (cellRef sub_mod (libraryRef
work)))
...

Be sure that:
/1/ no other definition of 'sub_mod' exists inside TOP edif file. In
the case remove it.
/2/ 'libraryRef' names are the same in both EDIF files (here it is
'work')
/3/ 'viewRef' names are the same in both EDIF files (here it is
'def_arch').

Hope this help.

Fabio
 
The VHDL part has been synthesised using Synplify, producing well-
looking EDIF. Then, I tried to compile (and I hoped then to P&R) the
two .edn files using Actel Designer. However, here comes the failure.
Click to expand...

One thing worth noting -- in the options for Synplify, you can make it
output tech-mapped Verilog or tech-mapped VHDL. I tend to use those
options, myself, when debugging designs, and it sounds like doing so
in your case could you help to find the source of the disconnected
instances.


regards,
Kris
 
Hello Marek,

Can you explain what you exactly did in your design, so you succefully ca
compile a VHDL with an EDN file?

I have an edn top design, created by presicion, and a UART VHDL core o
Actel, which I need to complie them both in my design.

Thank you in advanced,

Moran.

Hello, Daniel,

There are some challenges in merging EDIF netlists with Designer upon
import. I would let Synplify do the merging for you. Just have your
netlist in VHDL format and add it as an other source file. You can use
the edn2vhdl tool to create the VHDL netlist.

thank you for your answer. This is the problem: I need to bypass
synthesis step, since I am afraid, that some evil optimization could
damage my design. Even if it would work one, I have no guarantee, that
in next Synplify release it will result in exactly the same output
netlist.

However, I have been told the solution by Actel technical support, so
I am forwarding the reply:
-----
From Sagar.Gosavi@microsemi.com Tue Jan 4 10:51:54 2011
Date: Tue, 4 Jan 2011 15:21:54 +0530
From: "Gosavi, Sagar" <Sagar.Gosavi@microsemi.com
To: Marek Peca
Subject: RE: Actel Designer: how to compile VHDL top & EDIF submodule
together?:
489394-344304373

Hi Marek,

Thanks for contacting Actel Tech Support.

Can you please send me the design files for this project so that I
can understand the scenario better?

Between, if I understand the situation; are you observing some errors
like:

Error: CMP002: Net: CNT_16[0] is not driven
Error: CMP002: Net: CNT_16[1] is not driven
Error: CMP002: Net: CNT_16[2] is not driven
Error: CMP002: Net: CNT_16[3] is not driven

Also, if you find syn_black_box in your top level edn, kindly replace
it with the instance name of your subcircuit edn.

Note: The library name, cell name and the view name of the lower
level cell/edn has to match in its instantiation in the upper (in
this case, the top level) level

If above solution doesn't help, please send me your Project, so that
I can debug this issue better.

Have a great day ahead!

Thanks and Regards,
Sagar Gosavi
-----

So I have changed the library name to "work" and view name to
"syn_black_box" and now it works as expected, the Designer now
produces reasonably looking composite netlist. The EDIF excerpt looks
like:

(library work
(edifLevel 0)
(technology (numberDefinition))
(cell my_strange_circuit
(cellType GENERIC)
(view syn_black_box (viewType NETLIST)

...etc.


Greetings,
Marek
Click to expand...


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