actel blockram the easy way?

[Jason Zheng]

Is there an easy to use Actel's internal ram without going to coregen?
I'm concerned about compatibility issues if I have to use coregen.

thanks in advance.

 

[Ken McElvain]

We use the same inferencing independent of the target FPGA. The
differences are in how we map the inferred abstract RAM to the
target FPGA.

- Ken McElvain
Synplicity, Inc.


neilla@ewst.co.uk wrote:

Well in the release notes for Synplify 8.0A (downloadable from the
Actel website) it has the following:

For the Actel ProAsic Plus family, the synthesis software now extracts
single-port and dualport versions of the following RAM configurations:

SA Synchronous write, asynchronous read
SST Synchronous write, synchronous read, transparent output
SSR Synchronous write, synchronous read, registered output

For RAMS that are bigger than the basic block size of 256x9, the
software infers them by cascading similar kinds of basic blocks. For
wider RAMs, the software cascades basic blocks so that the same kinds
of inputs are tied together. For deeper RAMs, the software cascades
basic blocks and uses decoding logic.


So it looks like it is now possible to infer the RAMs, but I haven't
tried it yet, so am not sure how good it is, or what the HDL template
required is.

 

[Hans]

Hi Jason,

You can also use Precision (2005 and later) to infer synchronous memory. The
code below is what I used on my core although I am not sure this is the
approved template.

-- Actel Synchronous Memory
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity ssram is
port(
clk : in std_logic;
din128 : in std_logic_vector (127 downto 0);
addr : in std_logic_vector (3 downto 0);
we : in std_logic;
dout128 : out std_logic_vector (127 downto 0)
);
end ssram ;


architecture rtl of ssram is

type mem_type is array (15 downto 0) of std_logic_vector(127 downto 0) ;
signal mem : mem_type;

begin

singleport : process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
mem(conv_integer(addr)) <= din128;
else
dout128 <= mem(conv_integer(addr));
end if ;
end if;
end process singleport;

end architecture rtl;

Regards,
Hans.
www.ht-lab.com


"Jason Zheng" <xin.zheng@jpl.nasa.gov> wrote in message
news:d43ojt$on9$1@nntp1.jpl.nasa.gov...

Is there an easy to use Actel's internal ram without going to coregen? I'm
concerned about compatibility issues if I have to use coregen.

thanks in advance.

 

Well in the release notes for Synplify 8.0A (downloadable from the
Actel website) it has the following:

For the Actel ProAsic Plus family, the synthesis software now extracts
single-port and dualport versions of the following RAM configurations:

SA Synchronous write, asynchronous read
SST Synchronous write, synchronous read, transparent output
SSR Synchronous write, synchronous read, registered output

For RAMS that are bigger than the basic block size of 256x9, the
software infers them by cascading similar kinds of basic blocks. For
wider RAMs, the software cascades basic blocks so that the same kinds
of inputs are tied together. For deeper RAMs, the software cascades
basic blocks and uses decoding logic.


So it looks like it is now possible to infer the RAMs, but I haven't
tried it yet, so am not sure how good it is, or what the HDL template
required is.