aclr to FIFO

Hi all,

I am using Altera IP core for a dual-clock FIFO. I want to assert the
'async clear' port of the FIFO every time it gets full. The simplest
design I thought can be using the 'full' or 'almost full' as a control
to select aclr. However, this creates a feedback loop from output to
the input, which is probably a bad design. Is there a better way to do
that?

 

[Ben Jones]

I want to assert the 'async clear' port of the FIFO every time it gets
full.

Nooooooooooooooooooooooooooooooooooooooooooooooooooooo!

 

Ben Jones wrote:

I want to assert the 'async clear' port of the FIFO every time it gets
full.

Nooooooooooooooooooooooooooooooooooooooooooooooooooooo!

Well, sooooooooooooooooooooo...I got workaround the problem. I noted
that when the FIFO gets full it disables the rdreq signal. So I don't
read any new data thereafter. That solves my problem.