Achieving the timing

[rsk]

Hi friends,
These are my doubts
If we are not getting the timing at layout level tehn what do we have
to do for achiving the timing?

How to improve the frequency of the given optimized code?

Thanks to one and all who are helping in clarifying my doubts.

bye friends
ravi...

 

[ka]

On Fri, 16 Apr 2004 10:42:51 -0400, "rsk" <krs_1980@yahoo.co.in>
wrote:

Hi friends,
These are my doubts
If we are not getting the timing at layout level tehn what do we have
to do for achiving the timing?

How to improve the frequency of the given optimized code?

The answer changes all the way from "swap the inputs of this nand2
gate" to "add a pipeline register in this path" to "re-implement this
algorithm" depending on how badly you're missing timing. There are
many intermediate steps such as buffering high fanout nets,
duplicating registers, moving cells to reduce wire load etc etc.