Acek 1K - Quartus II - timing issues

[Kumaran]

Hi all,
I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
development using Leonardo Spectrum synthesizer(2002) and Max +2. My
license for leonardo expired, and I decided to use Quartus II(v3.0).
When I compile using Quartus, Iam getting a negative slack time for
one of my clock. when I compiled the same FPGA code using LS and Max
+2, I did not have any timing issues . In the compiler settings, I
have enabled the "optimize i/o cell register placement for timing"
option. I also tried different synthesis tool in quartus (FPGA
express, LS,..) but I could not get the timing right. Can anyone help
me?

Thanks,

Kumaran

 

[Manfred Balik]

It looks like you didn't use the internal Clock-Network.
Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have
the same delays of clock signal to each gate.
Manfred


"Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag
news:40f2d3e9.0311171247.ab73d04@posting.google.com...

Hi all,
I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
development using Leonardo Spectrum synthesizer(2002) and Max +2. My
license for leonardo expired, and I decided to use Quartus II(v3.0).
When I compile using Quartus, Iam getting a negative slack time for
one of my clock. when I compiled the same FPGA code using LS and Max
+2, I did not have any timing issues . In the compiler settings, I
have enabled the "optimize i/o cell register placement for timing"
option. I also tried different synthesis tool in quartus (FPGA
express, LS,..) but I could not get the timing right. Can anyone help
me?

Thanks,

Kumaran

 

[Kumaran]

Hi Manfred,
Thanks for your response. I am using the dedicated clock pin 79. I had
a look at other threads for optimizing the speed. Some one mentioned
that by increasing the seed in the fitter setting might increase the
speed, but, they also mentioned that there will only be a slight
improvement, and I saw a slight increase in the speed(not good
enough). Any other suggestions? Thanks for your time.

Thanks,
Kumaran

"Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<3fb9d94f$0$18702$3b214f66@tunews.univie.ac.at>...

It looks like you didn't use the internal Clock-Network.
Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have
the same delays of clock signal to each gate.
Manfred


"Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag
news:40f2d3e9.0311171247.ab73d04@posting.google.com...
Hi all,
I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
development using Leonardo Spectrum synthesizer(2002) and Max +2. My
license for leonardo expired, and I decided to use Quartus II(v3.0).
When I compile using Quartus, Iam getting a negative slack time for
one of my clock. when I compiled the same FPGA code using LS and Max
+2, I did not have any timing issues . In the compiler settings, I
have enabled the "optimize i/o cell register placement for timing"
option. I also tried different synthesis tool in quartus (FPGA
express, LS,..) but I could not get the timing right. Can anyone help
me?

Thanks,

Kumaran

 

[rickman]

If you are going to play with the seed, you need to try several settings
before you can say it won't work.

I once worked on a real b--ch of a design and my coworker set up a
script that would run multiple passes overnight. That was the only way
we ever got the thing working. he also had to write AWK scripts to
parse the timing results since this was MaxPlus2 and the thing pretty
well sucked for timing analysis. I believe Quartus is much better now.
But it left a bad taste in my mouth for Altera software. I'll get over
it some day...


Kumaran wrote:

Hi Manfred,
Thanks for your response. I am using the dedicated clock pin 79. I had
a look at other threads for optimizing the speed. Some one mentioned
that by increasing the seed in the fitter setting might increase the
speed, but, they also mentioned that there will only be a slight
improvement, and I saw a slight increase in the speed(not good
enough). Any other suggestions? Thanks for your time.

Thanks,
Kumaran

"Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<3fb9d94f$0$18702$3b214f66@tunews.univie.ac.at>...
It looks like you didn't use the internal Clock-Network.
Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have
the same delays of clock signal to each gate.
Manfred


"Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag
news:40f2d3e9.0311171247.ab73d04@posting.google.com...
Hi all,
I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
development using Leonardo Spectrum synthesizer(2002) and Max +2. My
license for leonardo expired, and I decided to use Quartus II(v3.0).
When I compile using Quartus, Iam getting a negative slack time for
one of my clock. when I compiled the same FPGA code using LS and Max
+2, I did not have any timing issues . In the compiler settings, I
have enabled the "optimize i/o cell register placement for timing"
option. I also tried different synthesis tool in quartus (FPGA
express, LS,..) but I could not get the timing right. Can anyone help
me?

Thanks,

Kumaran

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Vaughn Betz]

Hi Manfred,

Here are a few things you can try to meet timing:

1. Turn off "optimize i/o cell register placement for timing". That
option enables some aggressive optimizations for registered IO timing.
These optimizations can hurt internal clock frequencies (fmax). If
you are meeting your IO (Tsu & Tco) timing, but missing a clock timing
constraint, turning this option off may help.

2. Changing the fitter seed can let you search for a better fit.
Usually things only improve a few % if you search over several seeds,
but on some designs the gains can be larger.

3. You can automatically search for a better fit with the Design
Space Explorer (DSE) script that ships with Quartus. It will
automatically sweep the fitter seed for you, and turn on some hidden
try-harder options for placement, and save the best fit. For newer
familes like Stratix & Cyclone, it will also experiment with different
forms of physical synthesis and register packing, but those
optimizations are not available for the ACEX 1K family.

To use DSE type:

quartus_sh -t [quartus_install_dir]/bin/tcl_scripts/dse.tcl

It pops up a simple, self-explanatory GUI.

4. It sounds like you are using Quartus for synthesis. Make sure you
have "default logic synthesis style" = speed selected (this is the
default). It's under Settings->Default Logic Options.

5. Make sure you've set all your timing constraints.

6. Send us the design, and we can check if there is some poor
optimization going on in either synthesis or the fitter.

Hope this helps.

Vaughn
Altera


rickman <spamgoeshere4@yahoo.com> wrote in message news:<3FBB0854.A9C37455@yahoo.com>...

If you are going to play with the seed, you need to try several settings
before you can say it won't work.

I once worked on a real b--ch of a design and my coworker set up a
script that would run multiple passes overnight. That was the only way
we ever got the thing working. he also had to write AWK scripts to
parse the timing results since this was MaxPlus2 and the thing pretty
well sucked for timing analysis. I believe Quartus is much better now.
But it left a bad taste in my mouth for Altera software. I'll get over
it some day...


Kumaran wrote:

Hi Manfred,
Thanks for your response. I am using the dedicated clock pin 79. I had
a look at other threads for optimizing the speed. Some one mentioned
that by increasing the seed in the fitter setting might increase the
speed, but, they also mentioned that there will only be a slight
improvement, and I saw a slight increase in the speed(not good
enough). Any other suggestions? Thanks for your time.

Thanks,
Kumaran

"Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<3fb9d94f$0$18702$3b214f66@tunews.univie.ac.at>...
It looks like you didn't use the internal Clock-Network.
Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have
the same delays of clock signal to each gate.
Manfred


"Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag
news:40f2d3e9.0311171247.ab73d04@posting.google.com...
Hi all,
I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
development using Leonardo Spectrum synthesizer(2002) and Max +2. My
license for leonardo expired, and I decided to use Quartus II(v3.0).
When I compile using Quartus, Iam getting a negative slack time for
one of my clock. when I compiled the same FPGA code using LS and Max
+2, I did not have any timing issues . In the compiler settings, I
have enabled the "optimize i/o cell register placement for timing"
option. I also tried different synthesis tool in quartus (FPGA
express, LS,..) but I could not get the timing right. Can anyone help
me?

Thanks,

Kumaran

--

 

[Kumaran]

Hi Vaughn,
Thanks for the information. I tried DSE, and I am geeting and error
saying "Error: DSE does not support the ACEX1K family!".

1. Turn off "optimize i/o cell register placement for timing". That
option enables some aggressive optimizations for registered IO timing.
These optimizations can hurt internal clock frequencies (fmax). If
you are meeting your IO (Tsu & Tco) timing, but missing a clock timing
constraint, turning this option off may help.
Yes, Iam meeting the IO (Tsu & Tco) timing. I turned of the "optimize

i/o cell register placement for timing", but it did not make any
difference.

4. It sounds like you are using Quartus for synthesis. Make sure you
have "default logic synthesis style" = speed selected (this is the
default). It's under Settings->Default Logic Options
Did you mean optimization technique? The optimization technique is set

for speed.

5. Make sure you've set all your timing constraints.
I have set all my timing constraints.

I could synthesize my code for Acex 1K100 using Leonardo without any
timing issues. I used MAx +2 to complie the EDIF file generated by
Leonardo. By using quartus, is there anyway that I could get the same
speed that I got from LS and max +2? Thanks for your time.

Thanks,

Kumaran


vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0311192112.253d35a@posting.google.com>...

Hi Manfred,

Here are a few things you can try to meet timing:

1. Turn off "optimize i/o cell register placement for timing". That
option enables some aggressive optimizations for registered IO timing.
These optimizations can hurt internal clock frequencies (fmax). If
you are meeting your IO (Tsu & Tco) timing, but missing a clock timing
constraint, turning this option off may help.

2. Changing the fitter seed can let you search for a better fit.
Usually things only improve a few % if you search over several seeds,
but on some designs the gains can be larger.

3. You can automatically search for a better fit with the Design
Space Explorer (DSE) script that ships with Quartus. It will
automatically sweep the fitter seed for you, and turn on some hidden
try-harder options for placement, and save the best fit. For newer
familes like Stratix & Cyclone, it will also experiment with different
forms of physical synthesis and register packing, but those
optimizations are not available for the ACEX 1K family.

To use DSE type:

quartus_sh -t [quartus_install_dir]/bin/tcl_scripts/dse.tcl

It pops up a simple, self-explanatory GUI.

4. It sounds like you are using Quartus for synthesis. Make sure you
have "default logic synthesis style" = speed selected (this is the
default). It's under Settings->Default Logic Options.

5. Make sure you've set all your timing constraints.

6. Send us the design, and we can check if there is some poor
optimization going on in either synthesis or the fitter.

Hope this helps.

Vaughn
Altera


rickman <spamgoeshere4@yahoo.com> wrote in message news:<3FBB0854.A9C37455@yahoo.com>...
If you are going to play with the seed, you need to try several settings
before you can say it won't work.

I once worked on a real b--ch of a design and my coworker set up a
script that would run multiple passes overnight. That was the only way
we ever got the thing working. he also had to write AWK scripts to
parse the timing results since this was MaxPlus2 and the thing pretty
well sucked for timing analysis. I believe Quartus is much better now.
But it left a bad taste in my mouth for Altera software. I'll get over
it some day...


Kumaran wrote:

Hi Manfred,
Thanks for your response. I am using the dedicated clock pin 79. I had
a look at other threads for optimizing the speed. Some one mentioned
that by increasing the seed in the fitter setting might increase the
speed, but, they also mentioned that there will only be a slight
improvement, and I saw a slight increase in the speed(not good
enough). Any other suggestions? Thanks for your time.

Thanks,
Kumaran

"Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<3fb9d94f$0$18702$3b214f66@tunews.univie.ac.at>...
It looks like you didn't use the internal Clock-Network.
Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have
the same delays of clock signal to each gate.
Manfred


"Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag
news:40f2d3e9.0311171247.ab73d04@posting.google.com...
Hi all,
I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my
development using Leonardo Spectrum synthesizer(2002) and Max +2. My
license for leonardo expired, and I decided to use Quartus II(v3.0).
When I compile using Quartus, Iam getting a negative slack time for
one of my clock. when I compiled the same FPGA code using LS and Max
+2, I did not have any timing issues . In the compiler settings, I
have enabled the "optimize i/o cell register placement for timing"
option. I also tried different synthesis tool in quartus (FPGA
express, LS,..) but I could not get the timing right. Can anyone help
me?

Thanks,

Kumaran

--

 

[Vaughn Betz]

Hi Kumaran,

My replies below.

Vaughn

kumaran@trlabs.ca (Kumaran) wrote in message news:<40f2d3e9.0311200917.48805134@posting.google.com>...

Hi Vaughn,
Thanks for the information. I tried DSE, and I am geeting and error
saying "Error: DSE does not support the ACEX1K family!".

Apparently it didn't in QII 3.0. Sorry. I tried it in 4.0 and it
worked, so I assumed it did in 3.0 as well, but apparently it was only
recently ported to the ACEX 1K family. QII 4.0 will be out in 2-3
months. Until then, you can try manually changing the fitter seed, as
a poor man's DSE.
It's unlikely to help you much if the problem is poor synthesis making
you very far from timing though.

1. Turn off "optimize i/o cell register placement for timing". That
option enables some aggressive optimizations for registered IO
timing. These optimizations can hurt internal clock frequencies
(fmax). If you are meeting your IO (Tsu & Tco) timing, but missing
a clock timing constraint, turning this option off may help.
Yes, Iam meeting the IO (Tsu & Tco) timing. I turned of the "optimize
i/o cell register placement for timing", but it did not make any
difference.

Ok. Either you don't have registered IOs (in which case that
algorithm does nothing) or it's working well and not hurting your
Fmax.

4. It sounds like you are using Quartus for synthesis. Make sure
you have "default logic synthesis style" = speed selected (this is
the default). It's under Settings->Default Logic Options
Did you mean optimization technique? The optimization technique is set
for speed.

Yes, it is called Optimization Technique in QII 3.0. Sorry, the
version on my computers is 4.0 (in development), and we renamed the
option there.

5. Make sure you've set all your timing constraints.
I have set all my timing constraints.

I could synthesize my code for Acex 1K100 using Leonardo without any
timing issues. I used MAx +2 to complie the EDIF file generated by
Leonardo. By using quartus, is there anyway that I could get the same
speed that I got from LS and max +2? Thanks for your time.

Since you're using a different synthesis tool and a newer place and
route tool, there's no way to guarantee the same timing. Mostly QII
beats MaxPlus2 handily for 10K designs, but there are always a few
designs it does worse on.

If your speed is considerably worse, I suspect you are seeing a
synthesis quality problem, since you switched synthesis tools. If you
look at the critical path from the timing analyzer output, and
double-click on each hop in the critical path, you can see if

1. There are a lot of hops on the critical path (more than there were
in MaxPlusII). That probably indicates poor synthesis. You may be
able to re-code your HDL to get better synthesis. Or you could
synthesize with Leonardo and bring that into Quartus, since it sounds
like you got good results with Leonardo.

2. There aren't that many hops (logic levels) on the critical path,
but they use a lot of interconnect on each hop. This indicates poor
place & route, and changing the fitter seed may help.

If you generate a .qar of your design and send it in I'll file a
software problem report on it, and hopefully we can find some
optimization flaw. Sending in what timing you achieved in MaxPlus2
would also be helpful. But without seeing the design I'm out of
ideas.

Regards,

Vaughn
Altera