J
Jason D. Bakos
Guest
Hi everyone!
I have a generic question about noise modeling. My research group has
developed high-speed off-chip drivers/receivers as well as encoding
techniques for high-speed PCB chip-to-chip digital signaling (1-10 inch
range). We have implemented this technology with the IBM SiGe 5HP process
and did extensive simulation and testing. However, I would really like to
come up with some more accurate noise modeling techniques to determine
effects of noise on our chip-to-chip links.
Currently, I run simulations with Analog Environment 4.4.6 using extracted
layout and aggressive models for the package and PCB trace transmission
lines. I have also created Verilog-A voltage/current sources for adding
parameterized additive white Gaussian noise to the transmission lines
(simulating common-mode noise), to the power supply (simulating supply
noise), and to the driver bias input (simulating bias noise). From what I
understand, AWGN is extremely naive for simulating noise -- especially since
I don't even know which parameters to use, such as standard deviation. What
I really need are better noise models.
For example, when searching related literature, it is clear that there are 3
main sources of noise for LSI chips. First, there's direct radiation from
the chip surface. This comes from chip traces acting as antennas. Second,
there's noise from signal ports, which is typically minimized with IBIS
models (although I'm not familiar with IBIS models). Third, there's power
supply noise originating from on-chip. This is considered to be the most
significant and most devastating type of noise.
My question: where should I look for better models for simulating on-chip
noise and/or PCB trace noise in order to build the most accurate simulation
test bench for our signaling technology? We assume our signaling technology
is best used in processor-to-memory applications. Is it best to use
dependent or independent noise sources?
Thanks!
-Jason
I have a generic question about noise modeling. My research group has
developed high-speed off-chip drivers/receivers as well as encoding
techniques for high-speed PCB chip-to-chip digital signaling (1-10 inch
range). We have implemented this technology with the IBM SiGe 5HP process
and did extensive simulation and testing. However, I would really like to
come up with some more accurate noise modeling techniques to determine
effects of noise on our chip-to-chip links.
Currently, I run simulations with Analog Environment 4.4.6 using extracted
layout and aggressive models for the package and PCB trace transmission
lines. I have also created Verilog-A voltage/current sources for adding
parameterized additive white Gaussian noise to the transmission lines
(simulating common-mode noise), to the power supply (simulating supply
noise), and to the driver bias input (simulating bias noise). From what I
understand, AWGN is extremely naive for simulating noise -- especially since
I don't even know which parameters to use, such as standard deviation. What
I really need are better noise models.
For example, when searching related literature, it is clear that there are 3
main sources of noise for LSI chips. First, there's direct radiation from
the chip surface. This comes from chip traces acting as antennas. Second,
there's noise from signal ports, which is typically minimized with IBIS
models (although I'm not familiar with IBIS models). Third, there's power
supply noise originating from on-chip. This is considered to be the most
significant and most devastating type of noise.
My question: where should I look for better models for simulating on-chip
noise and/or PCB trace noise in order to build the most accurate simulation
test bench for our signaling technology? We assume our signaling technology
is best used in processor-to-memory applications. Is it best to use
dependent or independent noise sources?
Thanks!
-Jason