Accessing Simulator Event Queue!

[Hrh]

Greetings all Verilig fans,

I don't know much about Verilog but I have heard Verilog simulation
engines often use event driven based simulation techniques. Is there a
way to access
event queue of a verilog simulator like ncverilog? My understanding is
that PLI/VPI may allow this. Any hint, idea, or help?

Bests

Hrh.

 

[Swapnajit Mittra]

hamidrezah@yahoo.com (Hrh) wrote in message news:<e21cb992.0308221312.436b6390@posting.google.com>...

Greetings all Verilig fans,

I don't know much about Verilog but I have heard Verilog simulation
engines often use event driven based simulation techniques. Is there a
way to access
event queue of a verilog simulator like ncverilog? My understanding is
that PLI/VPI may allow this. Any hint, idea, or help?

Bests

Hrh.

The hint here would be: just say no.

There is no reason why you need to access the event queue
under normal circumstances. All of your design or verification
codes should be aware of the fact that you must not assume any
control over the event queue beyond what has been already
provided by the language constructs (blocking vs non-blocking
assignments, for example).

There is a way to access the time queue, for a different
reason, using vpi. See vpi_get_time() and vpi_iterate()
for more details.

- Swapnajit.
--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
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http://www.angelfire.com/ca/verilog/