D
daluu
Guest
I'm just learning Verilog in my Digital Design class. We focus more on
module design using Verilog than the actual verilog language.
I see these lines in code in our lab projects:
reg [N_channel*Data_width-1:0] in_tb_array[999:0];
...
...
Result_array <= [Data_width-1:0] in_tb_array;
This line gave compile problems in ModelSim.
I would believe by traditional programming construct the way to write it
the array assignment would be:
Result_array <= in_tb_array[Data_width-1:0];
This didn't give any compile errors. It appears to work in simulation, so
I just wanted to verify that my line of code is correct or not.
module design using Verilog than the actual verilog language.
I see these lines in code in our lab projects:
reg [N_channel*Data_width-1:0] in_tb_array[999:0];
...
...
Result_array <= [Data_width-1:0] in_tb_array;
This line gave compile problems in ModelSim.
I would believe by traditional programming construct the way to write it
the array assignment would be:
Result_array <= in_tb_array[Data_width-1:0];
This didn't give any compile errors. It appears to work in simulation, so
I just wanted to verify that my line of code is correct or not.