Access to internal signals in modules

[Brian Dam Pedersen]

In Icarus Verilog I am allowed to write something along the lines of

module counter (out,clk);

output [4:0] out;
input clk;

reg [4:0] cnt=0;

assign out = cnt + 2;

always @ (posedge clk)
cnt <= cnt + 2;
endmodule

module test(count_res_p2,count_res,clk);

input clk;


counter C(count_res_p2,clk);
assign count_res = C.cnt;
endmodule

The last assignment can be useful e.g. for gleaning into a module during
test. Now I want this to synthesize in xst (Webpack 7.1i). While it
seems to synthesize, count_res remains stuck at 0. Why is this ? Is
there anyway to do this in xst ?

Regards

-- Brian

 

[unfrostedpoptart]

Brian Dam Pedersen wrote:

In Icarus Verilog I am allowed to write something along the lines of

input clk;


counter C(count_res_p2,clk);
assign count_res = C.cnt; //******** hierachical reference
endmodule

The last assignment can be useful e.g. for gleaning into a module during
test. Now I want this to synthesize in xst (Webpack 7.1i). While it
seems to synthesize, count_res remains stuck at 0. Why is this ? Is
there anyway to do this in xst ?

These references through a hierarchy are a cheat that Verilog provides
to help in verification. It's not synthesizable. You need to add
ports and wires to your module to get down to the signal/module you are
trying to connect to. Again, you can't use this technique to
synthesizable code. Maybe you are new to Verilog and don't realize
that there's lots of stuff in the language that's only for simulation
and verification.

Now, you can have parts of your testbench poking around in your
synthesizable code using this technique. It can be used for internal
signal monitors. It can also be used to do things like presetting
ASIC/FPGA RAM contents. Be warned, though, that these are all cheats
and can get you into trouble. For example, a net you are trying to
peek at may be renamed or even optimized away during synthesis, causing
your gate-level simulation to fail.

In almost all cases, you don't need to use this - it just saves a
little effort or simulation time.

David

 

[Brian Dam Pedersen]

Thanks - this is what I suspected ...

Yes - I'm new to this, and this is as you write only something I use for
poking around. I was just trying to do "on-target debugging" I have
an event in a design that only occurs very rarely, and therefore takes a
loong time to find in normal simulation - but I guess I'll have to make
a "debug output" on my module instead to do what I want to do

-- Brian

unfrostedpoptart wrote:

Brian Dam Pedersen wrote:

In Icarus Verilog I am allowed to write something along the lines of


input clk;


counter C(count_res_p2,clk);
assign count_res = C.cnt; //******** hierachical reference
endmodule

The last assignment can be useful e.g. for gleaning into a module during
test. Now I want this to synthesize in xst (Webpack 7.1i). While it
seems to synthesize, count_res remains stuck at 0. Why is this ? Is
there anyway to do this in xst ?


These references through a hierarchy are a cheat that Verilog provides
to help in verification. It's not synthesizable. You need to add
ports and wires to your module to get down to the signal/module you are
trying to connect to. Again, you can't use this technique to
synthesizable code. Maybe you are new to Verilog and don't realize
that there's lots of stuff in the language that's only for simulation
and verification.

Now, you can have parts of your testbench poking around in your
synthesizable code using this technique. It can be used for internal
signal monitors. It can also be used to do things like presetting
ASIC/FPGA RAM contents. Be warned, though, that these are all cheats
and can get you into trouble. For example, a net you are trying to
peek at may be renamed or even optimized away during synthesis, causing
your gate-level simulation to fail.

In almost all cases, you don't need to use this - it just saves a
little effort or simulation time.

David