access internal signal on top level in VHDL

[anupam]

hi,
i want to force a value or read a value of an internal signal in VHDL .
That is possible with signal spy in model sim but i want to use ncsim .
Is it possible with ncsim without using any other language's interface
(like c or tcl)??
please suggest

 

[Ajeetha]

NC has similar feature called NC_MIRROR. You may also want to look at a
small package that we wrote a while back to work seamlessly across
simulators. I'm updating ti for VCSMX soon, but the one that works with
MTI/NC/Aldec is @

http://www.noveldv.com/eda/probe.zip

HTH
Ajeetha
www.noveldv.com

 

[Ralf Hildebrandt]

anupam wrote:

i want to force a value or read a value of an internal signal in VHDL .
That is possible with signal spy in model sim but i want to use ncsim .
Is it possible with ncsim without using any other language's interface
(like c or tcl)??

Its possible to do this with only plain VHDL:
http://groups.google.de/group/comp.lang.vhdl/browse_thread/thread/5716a6184a3e69bd/07232b67411adef8?lnk=st&q=Ralf+Hildebrandt+internal+signal+VHDL&rnum=5#07232b67411adef8

Ralf