Access inner signal in DUT

[xipn]

Hi all,
is it possible or exists any trick how to access inner signal of the
device under test or even signal concerned in any entity in DUT for
assert statement?
Or always I have to use some dedicated port?
Let me show it in the commented example:
------------------------------------------------------------
ENTITY testbench IS
END ENTITY testbench;

architecture sim of testbench is

SIGNAL a,b : STD_LOGIC;

begin
DUT : ENTITY work.main
PORT MAP (
A => a,
B => b);

process tb
-- some stimuli e.g.
a <= '1';
wait for ....
-- and now I would like to verify inner signal "temp"
-- of instance DUT
-- Exists something like following ?
-- The relation between instance DUT and
-- inner signal "temp" is expressed as DUT.temp (no record )
assert DUT.temp = '1' report "message" severity ...
end process tb;

end architecture sim;
------------------------------------------------------------
Entity main is
port (
A : in std_logic;
B : out std_logic
);
end main;

architecture syn of main is

signal temp : std_logic;

begin
-- ... an implemenation
end syn;
------------------------------------------------------------

Thanx for any opinion.

 

[Mark McDougall]

xipn wrote:

Hi all, is it possible or exists any trick how to access inner signal
of the device under test or even signal concerned in any entity in
DUT for assert statement? Or always I have to use some dedicated
port? Let me show it in the commented example:

Depends on your simulator.

ModelSim allows you to do this via a "signal spy" option.

Regards,
Mark

 

[Ralf Hildebrandt]

xipn wrote:

is it possible or exists any trick how to access inner signal of the
device under test or even signal concerned in any entity in DUT for
assert statement?

Create a package. Define inside this package a signal or a shared
variable. Link this package from every part of your design you want to
write to or read the signal / shared variable. Then use this this as you
would use it, if it would be declared inside your components.

The advantage of a shared variable is, that it is updated immediately
and is faster for simulation. The advantage of a signal is, that you can
use the 'event attribute on it.

Use a resolved data type, if you really have to write from different
locations to the signal.

Ralf

 

[Arash Salarian]

"xipn" <xipn@seznam.cz> wrote in message
news:dlbcmj$1upq$1@ns.felk.cvut.cz...

Hi all,
is it possible or exists any trick how to access inner signal of the
device under test or even signal concerned in any entity in DUT for assert
statement?
Or always I have to use some dedicated port?

Yes, you need a dedicated port. Why? Well, although you may find some
simulator specific solutions, but surely it is not standard and is a
practice that should be avoided unless it is too important to break the
portability of the codes. In general the problem is that this goes against
the basic philosophy of a clean VHDL model. Consider this: In a VHDL
project, you can have several entities. Each entity can have multiple
architecture that describe their behavior in different ways. Depending on
the configurations, different architectures for one entity can be selected
without touching any code in other architectures. To access the internal
signals/variables of one architecture by another architecture practically
binds these architectures together thorough a way outside the list of the
ports of the entity and breaks the whole separation of entity/architecture
concept.

Regards
Arash Salarian

 

[Harpreet]

Symphony Sonata allows you to do it. I myself needed it for verfication
purposes and also to look at the values taken up by the "variables" and
the "signals" defined inside the architecture. But you can avail this
facility only using professional edition of the software. You can ask
for a trial license for 30 days through the licensing wizard and extend
it if you need it for a longer duration.
Here's a link to their website:
http://www.symphonyeda.com

 

[Ralf Hildebrandt]

Harpreet wrote:

Symphony Sonata allows you to do it. ... But you can avail this
facility only using professional edition of the software.

Using a package with a signal / shared variable defined inside is free
and simulator-independent. It is even possible to use a generic
parameter, that selects, if the related logic will be implemented or not.

Ralf

 

[Ajeetha]

Hi,
http://www.noveldv.com/eda/probe.zip
http://www.verificationguild.org/modules.php?name=Downloads&d_op=viewdownload&cid=3

http://www.verificationguild.org/modules.php?name=Forums&file=viewtopic&t=453

Also read FAQ at www.vhdl.org/comp.lang.vhdl/

HTH
Ajeetha
www.novedv.com