Access custom VHDL types in TCL script

[Robert Schilling]

Hi Guys,

I'm having a custom type in VHDL:

type alu_op_code is (
ALU_OP_IDLE,
...
);

Now having a testbench written in TCL i wawnt to force signals of type
alu_op_code.

How to actually do that?
For std_logic data this is possible usng:

force signal_name '0'

But how to use that with custom types?

Thank you in advance!
Cheers Robert

 

[Brian Drummond]

On Sat, 07 Jun 2014 16:18:50 +0200, Robert Schilling wrote:

Hi Guys,

I'm having a custom type in VHDL:

type alu_op_code is (
ALU_OP_IDLE,
...
);

Now having a testbench written in TCL i wawnt to force signals of type
alu_op_code.

How to actually do that?

I think this is why my testbenches tend to be in VHDL.

If all else fails you can add a tedious but trivial VHDL wrapper to
interface between everything-is-an-integer land and a decent type system.

- Brian

 

[Robert Schilling]

If all else fails you can add a tedious but trivial VHDL wrapper to
interface between everything-is-an-integer land and a decent type system.

Thank you for your response. This is what I did meanwhile. It works but
I thought if there other possibilities.

Robert

--
Student of Telematics

 

[HT-Lab]

On 09/06/2014 09:43, Robert Schilling wrote:

If all else fails you can add a tedious but trivial VHDL wrapper to
interface between everything-is-an-integer land and a decent type system.

Thank you for your response. This is what I did meanwhile. It works but
I thought if there other possibilities.

Robert

--
Student of Telematics

Not sure what simulator you use but if you use Modelsim you can force
enumerated types.

signal opc : alu_op_code;

force -freeze /bla/opc ALU_OP_IDLE 0

Good luck,
Hans
www.ht-lab.com