Accesing a procedure

[ALuPin]

Hi,

I have a problem with accessing a procedure in a special manner:

Some background information:
I want to use a testbench in which I write the valid input data
(16bit) for my VHDL module under test into a ringbuffer. That is my
VHDL module gives out data (16 cleaned bit) after some pipelining
stages.
These output data should be compared with the data I have written into
my ringbuffer (The data in the ringbuffer are unstuffed, that is after
six consecutive ones the following zero is unstuffed. This unstuffing
function is of course also implemented in the VHDL module under test
itself.).
By the means of this object-oriented check I want to verify my module.


Here is my problem:

------------------------------------------------------------
architecture testb of xy is
signal t_Enable_in : std_logic;
signal t_Clk : std_logic;
signal t_Reset : std_logic;
signal t_In_data : std_logic_vector(15 downto 0);
constant history_size : integer := 1024;
signal t_history : std_logic_vector(history_size-1 downto 0);

....
procedure feed(signal d : in std_logic;
signal history : out std_logic_vector(history_size-1
downto 0)) is
variable ptr : integer range 0 to 1023;
variable n : integer range 0 to 6;
begin

if ((n=6) and (d='0')) then
null; --??? Does this exist in VHDL ?
else
history (ptr mod history_size) <= d;
end if;

if d='0' then
n:=0;
else
n:=n+1;
end if;


end feed;

begin
....
-------------------------------------------------------
-------------------------------------------------------
process(t_Reset, t_Clk)
begin
if t_Reset='1' then
t_history <= (others => '0');
elsif rising_edge(t_Clk) then
t_history <= t_history;
if t_Enable_in='1' then
for i in 15 downto 0 loop
feed(d => t_In_data(i),
history => t_history
);
end loop;
end if;
end if;
end process;
-------------------------------------------------------
-------------------------------------------------------
end testb;



I get the following error message (Modelsim5.7e)

# ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(134):
The actual for parameter d must denote a static signal name.
# ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(146):
VHDL Compiler exiting


How can I change that?

I would appreciate your time and help.

Kind regards
Andres V.

 

[Alan Fitch]

"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0404062349.2400d33@posting.google.com...

Hi,

I have a problem with accessing a procedure in a special manner:

Some background information:
I want to use a testbench in which I write the valid input data
(16bit) for my VHDL module under test into a ringbuffer. That is my
VHDL module gives out data (16 cleaned bit) after some pipelining
stages.
These output data should be compared with the data I have written
into
my ringbuffer (The data in the ringbuffer are unstuffed, that is
after
six consecutive ones the following zero is unstuffed. This
unstuffing
function is of course also implemented in the VHDL module under test
itself.).
By the means of this object-oriented check I want to verify my
module.


Here is my problem:

------------------------------------------------------------
architecture testb of xy is
signal t_Enable_in : std_logic;
signal t_Clk : std_logic;
signal t_Reset : std_logic;
signal t_In_data : std_logic_vector(15 downto 0);
constant history_size : integer := 1024;
signal t_history : std_logic_vector(history_size-1 downto 0);

...
procedure feed(signal d : in std_logic;
signal history : out std_logic_vector(history_size-1
downto 0)) is
variable ptr : integer range 0 to 1023;
variable n : integer range 0 to 6;
begin

if ((n=6) and (d='0')) then
null; --??? Does this exist in VHDL ?
else
history (ptr mod history_size) <= d;
end if;

if d='0' then
n:=0;
else
n:=n+1;
end if;


end feed;

begin
...
-------------------------------------------------------
-------------------------------------------------------
process(t_Reset, t_Clk)
begin
if t_Reset='1' then
t_history <= (others => '0');
elsif rising_edge(t_Clk) then
t_history <= t_history;
if t_Enable_in='1' then
for i in 15 downto 0 loop
feed(d => t_In_data(i),
history => t_history
);
end loop;
end if;
end if;
end process;
-------------------------------------------------------
-------------------------------------------------------
end testb;



I get the following error message (Modelsim5.7e)

# ** Error:
H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/s

imulation/modelsim/tb_decode_destuff_hs.vhd(134):

The actual for parameter d must denote a static signal name.
# ** Error:
H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/s

imulation/modelsim/tb_decode_destuff_hs.vhd(146):

VHDL Compiler exiting


How can I change that?

I would appreciate your time and help.

Kind regards
Andres V.

Hi Andres,
the problem is that an individual bit of a vector inside a
for loop is considered to be dynamic. In other words the indexing
is dynamic. This is because for loops are "dynamically elaborated".
Have a look at the section on "longest static prefix" in the
comp.lang.vhdl FAQ.

There are a number of possibilities

1) pass the whole vector into the procedure and test it all in one
go outside the for loop

2) re-write using a generate statement instead, i.e. create 16
parallel
processes, one per bit. The generate index is then constant (not
dynamically
elaborated) so it will be ok.

e.g.

g: for i in 15 downto 0 generate

process(t_Reset, t_Clk)
begin
if t_Reset='1' then
t_history <= (others => '0');
elsif rising_edge(t_Clk) then
t_history <= t_history;
if t_Enable_in='1' then
-- for i in 15 downto 0 loop
feed(d => t_In_data(i),
history => t_history
);
-- end loop;
end if;
end if;
end process;
end generate;

Hope this helps - the comp.lang.vhdl FAQ section at
http://www.eda.org/comp.lang.vhdl/FAQ1.html#drivers
is worth reading anyway,

regards

Alan
--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
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[Marija]

Hi, <p>here is what seems odd to me: <BR>
t_history &lt;= t_history. <BR>
I think you don't need to do this, <BR>
i.e. if t_Enable_in is not <BR>
asserted, this signal will keep <BR>
the old value. <p>The 'null' command exists in VHDL, <BR>
but I've never used it in this <BR>
way. Testbenches usually contain <BR>
checker procedures to check if the <BR>
output complies with the expected. <BR>
You can set the checker procedure <BR>
to notify you about the test <BR>
results by: <p>assert (condition_not_fulfilled) <BR>
report "test passed"; <BR>
assert (condition_fulfilled) <BR>
report "test failed"; <p>where condition means comparing <BR>
the expected output with the data <BR>
you collected from the output. <p>I hope I offered you at least a <BR>
hint <p>BR, <BR>
Marija