Accellera, OVL, and VHDL?

[geocon]

I downloaded OVL from Accellera's web site back in August (2005). It
was version 03.06.06 and it included both Verilog and VHDL assertions.
Yesterday (Sep 28, 2005), I went to Accelleras web page and it has a
link to download OVL V1 (1.1b) which is Verilog and SystemVerilog but
no VHDL assertions.
What happened to the OVL VHDL assertions?
I've searched the web and can't find any explaination.
Does anyone know what the deal is?

GeoCon

 

Hello George,

in the begining of this year Accellera re-organized OVL to be 3
committees; OVL-VSVA, OVL-PSL, and OVL-VHDL with the objective to
update the spec, libraries and interoperability. The most active
committee has been the OVL-VSVA committee and you might have seen
the result in the new Accellera Standard OVL library. To enable
VHDL users (who has access to mix-language verification engines)
to leverage the library until we have a VHDL version you will find
a VHDL package that can be used so far.

Please fell free to contact me if you need more details.
Thanks
Kenneth Larsen (OVL-VSVA Chair)


geocon wrote:

I downloaded OVL from Accellera's web site back in August (2005). It
was version 03.06.06 and it included both Verilog and VHDL assertions.
Yesterday (Sep 28, 2005), I went to Accelleras web page and it has a
link to download OVL V1 (1.1b) which is Verilog and SystemVerilog but
no VHDL assertions.
What happened to the OVL VHDL assertions?
I've searched the web and can't find any explaination.
Does anyone know what the deal is?

GeoCon

 

[geocon]

Thanks for responding to my questions Kenneth.
Any idea on a time frame for the OVL-VHDL committee to release a VHDL
version of OVL (i.e. weeks, months, years)?
I did find the "PACKAGE std_ovl" (in std_ovl.vhd) among the Verilog
files in my downloaded std_ovl (v1.1b). Unfortunately few of our
designers have access to a mixed-language simulator.
Regards,
George C.

kenneth_larsen@mentor.com wrote:

Hello George,

in the begining of this year Accellera re-organized OVL to be 3
committees; OVL-VSVA, OVL-PSL, and OVL-VHDL with the objective to
update the spec, libraries and interoperability. The most active
committee has been the OVL-VSVA committee and you might have seen
the result in the new Accellera Standard OVL library. To enable
VHDL users (who has access to mix-language verification engines)
to leverage the library until we have a VHDL version you will find
a VHDL package that can be used so far.

Please fell free to contact me if you need more details.
Thanks
Kenneth Larsen (OVL-VSVA Chair)


geocon wrote:
I downloaded OVL from Accellera's web site back in August (2005). It
was version 03.06.06 and it included both Verilog and VHDL assertions.
Yesterday (Sep 28, 2005), I went to Accelleras web page and it has a
link to download OVL V1 (1.1b) which is Verilog and SystemVerilog but
no VHDL assertions.
What happened to the OVL VHDL assertions?
I've searched the web and can't find any explaination.
Does anyone know what the deal is?

GeoCon