W
wilcn
Guest
Due to nowadays high-density PCB design, it usually impossible to
populate a test access for each nets. If a design has IEEE1149
compliant devices used, some access can be safely removed without
scarify the net coverage with the visibility and controllability
provided by the IOs of IEEE1149 compliant devices via the serial test
access ports. We have tools generate the test access list, and we want
to import the list into the Allegro, asking for the test access needed
during the place/route.
My problem is:
Wow can I make it?
What's more, I want also want to go further, I want to integrate the
design database automatically, to remove the test access requirement if
there's PTH devices' pin connected on the net, which can be used as
test access.
Thanks
populate a test access for each nets. If a design has IEEE1149
compliant devices used, some access can be safely removed without
scarify the net coverage with the visibility and controllability
provided by the IOs of IEEE1149 compliant devices via the serial test
access ports. We have tools generate the test access list, and we want
to import the list into the Allegro, asking for the test access needed
during the place/route.
My problem is:
Wow can I make it?
What's more, I want also want to go further, I want to integrate the
design database automatically, to remove the test access requirement if
there's PTH devices' pin connected on the net, which can be used as
test access.
Thanks