About textio

Z

Zhi

Guest
I am learning how to use textio. I wrote a program
src.txt
{00000000
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;


use ieee.std_logic_textio.all;
use std.textio.all;

entity check is
port (clk:in std_logic;
a:eek:ut std_logic_vector(7 downto 0));
end check;

architecture serial of check is
file from_file:text open READ_MODE is "src.txt";
file to_text:text open WRITE_MODE is " text1.txt";
begin
process (clk)
variable buf_out,buf_in:line;
variable num: std_logic_vector(7 downto 0):=(others=>'0');
begin
if clk'event and clk='1' then
while not ENDFILE(from_file)loop

READLINE(from_file,buf_out);
READ(buf_out,num);

a<= num;

WRITE (buf_in,num);
WRITELINE(to_text,buf_in);
end loop;
end if;
end process;
end serial;
Why the ModemSim always runs except I stop it.

When I simulate it in ModelSim, 'a' only shows the last value
(10000000) of the 'from_file'. If I remove the sensitivity list
(clk)
begin

while not ENDFILE(from_file)loop

READLINE(from_file,buf_out);
READ(buf_out,num);

a<= num;
wait for 10 ps;
WRITE (buf_in,num);
WRITELINE(to_text,buf_in);
end loop;

end process;
end serial;

The last value "10000000" cannot write into to_text. What is the
problem? And Simulation lasts 80 ps and shows each output value at
every 10 ps. When the clk is going to 90ns. The ModelSim is running
like going to stop.
 
if clk'event and clk='1' then
while not ENDFILE(from_file)loop

READLINE(from_file,buf_out);
READ(buf_out,num);

a<= num;

WRITE (buf_in,num);
WRITELINE(to_text,buf_in);
end loop;
The entire loop will be executed at the first rising edge of clk. I
Click to expand...
guess you want it to step a line each rising edge of clk. To do this you
can write something like this :
label : process -- no sensitivity list
begin
while (condition) loop
wait until rising_edge(clk);
-- do your thing
end loop;
clk_enable <= false; -- used to disable the clock generator
report "Reached end of test procedure.";
wait; -- suspend the process so it won't restart.
end process label;

If you use the "run -all" command in modelsim it will run as long as
there are events scheduled. Be sure to suspend all processes without a
sensitivity list.

For clock generation I use somthign like this :
process
begin
if clk_enable then
wait for 10 ns;
clk <= not clk;
else
wait;
end if;
end process;
 
Magne wrote:
if clk'event and clk='1' then
while not ENDFILE(from_file)loop

READLINE(from_file,buf_out);
READ(buf_out,num);

a<= num;

WRITE (buf_in,num);
WRITELINE(to_text,buf_in);
end loop;
The entire loop will be executed at the first rising edge of clk. I
guess you want it to step a line each rising edge of clk. To do this you
can write something like this :
label : process -- no sensitivity list
begin
while (condition) loop
wait until rising_edge(clk);
-- do your thing
end loop;
clk_enable <= false; -- used to disable the clock generator
report "Reached end of test procedure.";
wait; -- suspend the process so it won't restart.
end process label;

If you use the "run -all" command in modelsim it will run as long as
there are events scheduled. Be sure to suspend all processes without a
sensitivity list.

For clock generation I use somthign like this :
process
begin
if clk_enable then
wait for 10 ns;
clk <= not clk;
else
wait;
end if;
end process;
Click to expand...
Thanks Magne. I have noticed that and changed them.
 
On 28 avr, 22:54, Zhi <threeinchn...@gmail.com> wrote:
I am learning how to use textio. I wrote a program
src.txt
{00000000
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

use ieee.std_logic_textio.all;
use std.textio.all;

entity check is
port (clk:in std_logic;
a:eek:ut std_logic_vector(7 downto 0));
end check;

architecture serial of check is
file from_file:text open READ_MODE is "src.txt";
file to_text:text open WRITE_MODE is " text1.txt";
begin
process (clk)
variable buf_out,buf_in:line;
variable num: std_logic_vector(7 downto 0):=(others=>'0');
begin
if clk'event and clk='1' then
while not ENDFILE(from_file)loop

READLINE(from_file,buf_out);
READ(buf_out,num);

a<= num;

WRITE (buf_in,num);
WRITELINE(to_text,buf_in);
end loop;
end if;
end process;
end serial;
Why the ModemSim always runs except I stop it.

When I simulate it in ModelSim, 'a' only shows the last value
(10000000) of the 'from_file'. If I remove the sensitivity list
(clk)
begin

while not ENDFILE(from_file)loop

READLINE(from_file,buf_out);
READ(buf_out,num);

a<= num;
wait for 10 ps;
WRITE (buf_in,num);
WRITELINE(to_text,buf_in);
end loop;

end process;
end serial;

The last value "10000000" cannot write into to_text. What is the
problem? And Simulation lasts 80 ps and shows each output value at
every 10 ps. When the clk is going to 90ns. The ModelSim is running
like going to stop.
Click to expand...
hi , first of all i m a beginner for my test to find a solution i get
a result but ( for the last value it cant be write for the output

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;

entity check is
Port ( clk : in STD_LOGIC;
a : out STD_LOGIC_VECTOR (7 downto 0));
end check;

architecture Behavioral of check is
file from_file:text open READ_MODE is "src.txt";
file to_text:text open WRITE_MODE is " text1.txt";
begin
process
variable buf_out,buf_in:line;
variable num: std_logic_vector(7 downto 0):=(others=>'0');
begin
seq:loop
wait until clk'event and clk = '1';
exit seq when ENDFILE(from_file);
READLINE(from_file,buf_in);
READ(buf_in,num);
a <= num;
WRITE (buf_in,num);
WRITELINE(to_text,buf_in);
end loop;
end process;
end Behavioral;
 
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