About terms in hardware

[parag_paul@hotmail.com]

hi All
Sorry for a dumbo again
I want to know the meaning of the term " driven by a single
primitive"

For a wire that has a chance of getting driven somewhere down the
hierarchy or coerced to inout, how come we can be sure of driven of a
single primitive.

What is the meaning of the term 'wired logic" ,does it mean that there
are no registers in the design. Are registers synthesizable

 

[John_H]

<parag_paul@hotmail.com> wrote in message
news:1174497858.127118.310630@l75g2000hse.googlegroups.com...

hi All
Sorry for a dumbo again
I want to know the meaning of the term " driven by a single
primitive"

For a wire that has a chance of getting driven somewhere down the
hierarchy or coerced to inout, how come we can be sure of driven of a
single primitive.

What is the meaning of the term 'wired logic" ,does it mean that there
are no registers in the design. Are registers synthesizable

ECL is an example of "wire or" logic where a logic low is no drive - the
termination resistor pulls the output to the established low level; only an
active output drives the level high. If you connect two ECL outputs
together, neither drives and the termination resistor establishes a low. If
either or both ECL drivers are driving the common wire, the logic level will
be high. This is an example of wired logic.

Tristate logic works in a similar manner when a weak high drive is swamped
by a low drive for a normally pulled-high line. If no tristate buffers are
enabled, the pullup wins. If any single buffer is apply a logic-low drive,
its tendency is to swamp out any highs driven onto the bus. This behavior
was emulated in non-tristate logic for the "internal tristates" in Xilinx
Spartan-2 devices, for instance. The discussion of "swamping" to resolve
bus contention isn't always valid - if you switch from tristates to
open-drain outputs, the behavior always works. This is an example of a
"wired and."

To avoid contention, a wire needs one driver. Drivers come from primitives.
Modules can have outputs or inouts where - internal to that module -multiple
drivers come from multiple primitives. To "drill down" to know you only
have one driver, you need to verify there's only one bottom-level driver (or
primitive) sourcing that signal. If you know a module port is output only,
you still don't know that the wire is free from contention internal to the
module without drilling down to the primitive level.

 

[parag_paul@hotmail.com]

On Mar 21, 10:44 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

parag_p...@hotmail.com> wrote in message

news:1174497858.127118.310630@l75g2000hse.googlegroups.com...

hi All
Sorry for a dumbo again
I want to know the meaning of the term " driven by a single
primitive"

For a wire that has a chance of getting driven somewhere down the
hierarchy or coerced to inout, how come we can be sure of driven of a
single primitive.

What is the meaning of the term 'wired logic" ,does it mean that there
are no registers in the design. Are registers synthesizable

ECL is an example of "wire or" logic where a logic low is no drive - the
termination resistor pulls the output to the established low level; only an
active output drives the level high. If you connect two ECL outputs
together, neither drives and the termination resistor establishes a low. If
either or both ECL drivers are driving the common wire, the logic level will
be high. This is an example of wired logic.

Tristate logic works in a similar manner when a weak high drive is swamped
by a low drive for a normally pulled-high line. If no tristate buffers are
enabled, the pullup wins. If any single buffer is apply a logic-low drive,
its tendency is to swamp out any highs driven onto the bus. This behavior
was emulated in non-tristate logic for the "internal tristates" in Xilinx
Spartan-2 devices, for instance. The discussion of "swamping" to resolve
bus contention isn't always valid - if you switch from tristates to
open-drain outputs, the behavior always works. This is an example of a
"wired and."

To avoid contention, a wire needs one driver. Drivers come from primitives.
Modules can have outputs or inouts where - internal to that module -multiple
drivers come from multiple primitives. To "drill down" to know you only
have one driver, you need to verify there's only one bottom-level driver (or
primitive) sourcing that signal. If you know a module port is output only,
you still don't know that the wire is free from contention internal to the
module without drilling down to the primitive level.

Since I have no ready reference of ECL, <-- you mean emitter coupled
logic right.
I am software guy and have no knowledge of devices. Can you please
help me understand it in a functional view

 

[John_H]

<parag_paul@hotmail.com> wrote in message
news:1174527811.375736.79030@d57g2000hsg.googlegroups.com...

On Mar 21, 10:44 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
parag_p...@hotmail.com> wrote in message

news:1174497858.127118.310630@l75g2000hse.googlegroups.com...

hi All
Sorry for a dumbo again
I want to know the meaning of the term " driven by a single
primitive"

For a wire that has a chance of getting driven somewhere down the
hierarchy or coerced to inout, how come we can be sure of driven of a
single primitive.

What is the meaning of the term 'wired logic" ,does it mean that there
are no registers in the design. Are registers synthesizable

ECL is an example of "wire or" logic where a logic low is no drive - the
termination resistor pulls the output to the established low level; only
an
active output drives the level high. If you connect two ECL outputs
together, neither drives and the termination resistor establishes a low.
If
either or both ECL drivers are driving the common wire, the logic level
will
be high. This is an example of wired logic.

Tristate logic works in a similar manner when a weak high drive is
swamped
by a low drive for a normally pulled-high line. If no tristate buffers
are
enabled, the pullup wins. If any single buffer is apply a logic-low
drive,
its tendency is to swamp out any highs driven onto the bus. This
behavior
was emulated in non-tristate logic for the "internal tristates" in Xilinx
Spartan-2 devices, for instance. The discussion of "swamping" to resolve
bus contention isn't always valid - if you switch from tristates to
open-drain outputs, the behavior always works. This is an example of a
"wired and."

To avoid contention, a wire needs one driver. Drivers come from
primitives.
Modules can have outputs or inouts where - internal to that
module -multiple
drivers come from multiple primitives. To "drill down" to know you only
have one driver, you need to verify there's only one bottom-level driver
(or
primitive) sourcing that signal. If you know a module port is output
only,
you still don't know that the wire is free from contention internal to
the
module without drilling down to the primitive level.



Since I have no ready reference of ECL, <-- you mean emitter coupled
logic right.
I am software guy and have no knowledge of devices. Can you please
help me understand it in a functional view

You didn't have to *know* ECL to understand what I wrote in describing the
ECL (or tristate or open drain) behavior so I must not be seeing how I
didn't communicate properly.

What is unclear?
Are you unfamiliar with open drain behavior?
Do you know the results of driving against a pull-up or pull-down resistor
versos not driving against it?
Is the idea that a logic low will "swamp out" a logic high too foreign in my
words?


Bottome line: wire logic is where one logic level beats out the other when
there are multiple drivers onto one wire with conflicting values.
Depending on which level beats out the other, a "wire and" or "wire or" can
be realized.

 

[John_H]

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--------- -------- ---------

hi John
yes I am unfamilar with all the things that you wrote. I have never
touched anythign in elctronics. For us it is like trying to write a
software for the electrnics guys is becoming deifficlut if we dont
understand the underlying principles.
The other day we were disucssing the behavior of a verilog

#1 a=1;
#3 a=1;

Should the simulator make it a single assginment, removing the old
one. How does a s/w decide this ?
So can you suggest a book or web page where I can have a start atleast
with this things
-Parag

Sorry - I don't have good suggestions for 1) hardware fundamentals for
software engineers or 2) a good Verilog reference. If you search the
Verilog newsgroup for "book" you should find a few dozen recommendations
for one or two books. The basics of simulation cycles and scheduling
and the nuances of the timescale will all be noted in a decent Verilog text.