about slices in xilinx

M

mary

Guest
hi all,


i have a doubt regarding no.of slices in xlinx

what are slices?
what are LUT? in xilinx

1)the no.of slice constant in every version or does it vary?

2)can the area of an architecture be decreased if we say no.of slices ar
decreased.
is this type of approach is correct?
or
3) how can we say a area of architecture is decreased?

4)i am implementing project which is having the no.of slices in order o
hundreds.
where as the previous technique implemented have the no.of slices in orde
of thousands from this can we conclude that the area is decreased.


please kindly answer.



my mail id: marysowji.99@gmail.com





---------------------------------------
Posted through http://www.FPGARelated.com
 
On Apr 26, 10:07 pm, "mary" <marysowji.99@n_o_s_p_a_m.gmail.com>
wrote:
hi all,

i have a doubt regarding no.of slices in xlinx

what are slices?
what are LUT? in xilinx

1)the no.of slice constant in every version or does it vary?

2)can the area of an architecture be decreased if we say no.of slices are
decreased.
is this type of approach is correct?
or
3) how can we say a area of architecture is decreased?

4)i am implementing project which is having the no.of slices in order of
hundreds.
where as the previous technique implemented have the no.of slices in order
of thousands from  this can we conclude that the area is decreased.
Click to expand...
A LUT is a "look up table" and are how an FPGA implements
combinatorial logic. For all practical purposes it is a block of
memory with the logic inputs used as the address and the data output
used as the logic output. The memory contents defines that logic
function implemented. Is that what you are asking?

For a long time all LUTs in Xilinx parts had four inputs although they
did some funky things with multiplexers to allow two or even four of
the four input LUTS to be combined into five and even six input LUTS.
In some of the newer parts in the high end logic families they provide
six input LUTS. This is partly because the parts are getting so large
that, like the CPUs in PCs they are having trouble finding ways to use
the larger number of transistors. So they are making the LUTs
larger.

A slice is just a grouping of LUTs and FFs and some connective
structure into the repeated unit of the FPGA. The number of LUTs and
FFs vary with family. Originally LUTs had two LUTs and two FFs.
According to the manual "Each Virtex-6 FPGA slice contains four LUTs
and eight flip-flops", but they also use the term "Logic Cells" which
is not a countable entity in a part, it is a marketing number like
"gates".

Using the number of slices used is not a good metric for the size of a
design because if one LUT is used, the slice is counted as used.
Better to count the number of LUTs and FF used. You can have 100%
slice utilization and still fit more into a chip. But when 100% of
the LUTs and FFs are used, you will be hard pressed to add anything to
that design!

Rick
 
hi all,


i have a doubt regarding no.of slices in xlinx

what are slices?
what are LUT? in xilinx

1)the no.of slice constant in every version or does it vary?

2)can the area of an architecture be decreased if we say no.of slices are
decreased.
is this type of approach is correct?
or
3) how can we say a area of architecture is decreased?

4)i am implementing project which is having the no.of slices in order of
hundreds.
where as the previous technique implemented have the no.of slices i
order
of thousands from this can we conclude that the area is decreased.


please kindly answer.
Click to expand...
Watch and learn:
http://www.xilinx.com/training/fpga/virtex-6-slice-and-io-resources-video.htm


---------------------------------------
Posted through http://www.FPGARelated.com
 
On Apr 26, 8:40 pm, rickman <gnu...@gmail.com> wrote:
On Apr 26, 10:07 pm, "mary" <marysowji.99@n_o_s_p_a_m.gmail.com
wrote:



hi all,

i have a doubt regarding no.of slices in xlinx

what are slices?
what are LUT? in xilinx

1)the no.of slice constant in every version or does it vary?

2)can the area of an architecture be decreased if we say no.of slices are
decreased.
is this type of approach is correct?
or
3) how can we say a area of architecture is decreased?

4)i am implementing project which is having the no.of slices in order of
hundreds.
where as the previous technique implemented have the no.of slices in order
of thousands from  this can we conclude that the area is decreased.

A LUT is a "look up table" and are how an FPGA implements
combinatorial logic.  For all practical purposes it is a block of
memory with the logic inputs used as the address and the data output
used as the logic output.  The memory contents defines that logic
function implemented.  Is that what you are asking?

For a long time all LUTs in Xilinx parts had four inputs although they
did some funky things with multiplexers to allow two or even four of
the four input LUTS to be combined into five and even six input LUTS.
In some of the newer parts in the high end logic families they provide
six input LUTS.  This is partly because the parts are getting so large
that, like the CPUs in PCs they are having trouble finding ways to use
the larger number of transistors.  So they are making the LUTs
larger.

A slice is just a grouping of LUTs and FFs and some connective
structure into the repeated unit of the FPGA.  The number of LUTs and
FFs vary with family.  Originally LUTs had two LUTs and two FFs.
According to the manual "Each Virtex-6 FPGA slice contains four LUTs
and eight flip-flops", but they also use the term "Logic Cells" which
is not a countable entity in a part, it is a marketing number like
"gates".

Using the number of slices used is not a good metric for the size of a
design because if one LUT is used, the slice is counted as used.
Better to count the number of LUTs and FF used.  You can have 100%
slice utilization and still fit more into a chip.  But when 100% of
the LUTs and FFs are used, you will be hard pressed to add anything to
that design!

Rick
Click to expand...
The OP should thank you for doing their (class) homework for them.

RK
 
On Apr 27, 10:34 am, NeedCleverHandle <d_s_kl...@yahoo.com> wrote:
On Apr 26, 8:40 pm, rickman <gnu...@gmail.com> wrote:



On Apr 26, 10:07 pm, "mary" <marysowji.99@n_o_s_p_a_m.gmail.com
wrote:

hi all,

i have a doubt regarding no.of slices in xlinx

what are slices?
what are LUT? in xilinx

1)the no.of slice constant in every version or does it vary?

2)can the area of an architecture be decreased if we say no.of slices are
decreased.
is this type of approach is correct?
or
3) how can we say a area of architecture is decreased?

4)i am implementing project which is having the no.of slices in order of
hundreds.
where as the previous technique implemented have the no.of slices in order
of thousands from  this can we conclude that the area is decreased.

A LUT is a "look up table" and are how an FPGA implements
combinatorial logic.  For all practical purposes it is a block of
memory with the logic inputs used as the address and the data output
used as the logic output.  The memory contents defines that logic
function implemented.  Is that what you are asking?

For a long time all LUTs in Xilinx parts had four inputs although they
did some funky things with multiplexers to allow two or even four of
the four input LUTS to be combined into five and even six input LUTS.
In some of the newer parts in the high end logic families they provide
six input LUTS.  This is partly because the parts are getting so large
that, like the CPUs in PCs they are having trouble finding ways to use
the larger number of transistors.  So they are making the LUTs
larger.

A slice is just a grouping of LUTs and FFs and some connective
structure into the repeated unit of the FPGA.  The number of LUTs and
FFs vary with family.  Originally LUTs had two LUTs and two FFs.
According to the manual "Each Virtex-6 FPGA slice contains four LUTs
and eight flip-flops", but they also use the term "Logic Cells" which
is not a countable entity in a part, it is a marketing number like
"gates".

Using the number of slices used is not a good metric for the size of a
design because if one LUT is used, the slice is counted as used.
Better to count the number of LUTs and FF used.  You can have 100%
slice utilization and still fit more into a chip.  But when 100% of
the LUTs and FFs are used, you will be hard pressed to add anything to
that design!

Rick

The OP should thank you for doing their (class) homework for them.

RK
Click to expand...
Wow, I don't know homework can be done easily online today. The
question is, does he remember anything afterward ? I think he does
 
The question is, does he remember anything afterward ? I think he does
Click to expand...
Hmm. You could make him solve a (homework) excercise, to find out if
he does?
 
On Apr 27, 11:34 am, NeedCleverHandle <d_s_kl...@yahoo.com> wrote:
On Apr 26, 8:40 pm, rickman <gnu...@gmail.com> wrote:



On Apr 26, 10:07 pm, "mary" <marysowji.99@n_o_s_p_a_m.gmail.com
wrote:

hi all,

i have a doubt regarding no.of slices in xlinx

what are slices?
what are LUT? in xilinx

1)the no.of slice constant in every version or does it vary?

2)can the area of an architecture be decreased if we say no.of slices are
decreased.
is this type of approach is correct?
or
3) how can we say a area of architecture is decreased?

4)i am implementing project which is having the no.of slices in order of
hundreds.
where as the previous technique implemented have the no.of slices in order
of thousands from  this can we conclude that the area is decreased.

A LUT is a "look up table" and are how an FPGA implements
combinatorial logic.  For all practical purposes it is a block of
memory with the logic inputs used as the address and the data output
used as the logic output.  The memory contents defines that logic
function implemented.  Is that what you are asking?

For a long time all LUTs in Xilinx parts had four inputs although they
did some funky things with multiplexers to allow two or even four of
the four input LUTS to be combined into five and even six input LUTS.
In some of the newer parts in the high end logic families they provide
six input LUTS.  This is partly because the parts are getting so large
that, like the CPUs in PCs they are having trouble finding ways to use
the larger number of transistors.  So they are making the LUTs
larger.

A slice is just a grouping of LUTs and FFs and some connective
structure into the repeated unit of the FPGA.  The number of LUTs and
FFs vary with family.  Originally LUTs had two LUTs and two FFs.
According to the manual "Each Virtex-6 FPGA slice contains four LUTs
and eight flip-flops", but they also use the term "Logic Cells" which
is not a countable entity in a part, it is a marketing number like
"gates".

Using the number of slices used is not a good metric for the size of a
design because if one LUT is used, the slice is counted as used.
Better to count the number of LUTs and FF used.  You can have 100%
slice utilization and still fit more into a chip.  But when 100% of
the LUTs and FFs are used, you will be hard pressed to add anything to
that design!

Rick

The OP should thank you for doing their (class) homework for them.

RK
Click to expand...
Yeah, you may be right. But if test questions are asking about vague
things like "slices" then he needs a new professor.

Rick
 
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