about relational greater operator

[jitendra]

hi all,
if my code is like this:

module mod_greater(out, in0, in1);
input [7:0] in0, in1;
output [7:0] out;
assign out = in0 < in1;
endmodule

now, with simulating with Modelsim if one of the operand is
having x or
z value; the result out is having all bits x i.e. out =
8'bxxxxxxxx.
& while simulating with NC-SIM, the LSB bit comes x only & all
other
bits set to zero. i.e. the result is out = 8'b0000000x.
please tell me which one is true result.
& whose standards should be followed?
suggest me. looking for a positive reply from you all.
thanks n regards,
jiten

 

[Svilen Krustev]

Are you sure that out has to have a size [7:0] ?

jitendra wrote:

hi all,
if my code is like this:

module mod_greater(out, in0, in1);
input [7:0] in0, in1;
output [7:0] out;
output out;
assign out = in0 < in1;
endmodule

now, with simulating with Modelsim if one of the operand is
having x or
z value; the result out is having all bits x i.e. out =
8'bxxxxxxxx.
& while simulating with NC-SIM, the LSB bit comes x only & all
other
bits set to zero. i.e. the result is out = 8'b0000000x.
please tell me which one is true result.
& whose standards should be followed?
suggest me. looking for a positive reply from you all.
thanks n regards,
jiten

 

[Jonathan Bromley]

On 10 Oct 2005 06:16:39 -0700, "jitendra" <jitendra.jeet@gmail.com>
wrote:

hi all,
if my code is like this:

module mod_greater(out, in0, in1);
input [7:0] in0, in1;
output [7:0] out;
assign out = in0 < in1;
endmodule

now, with simulating with Modelsim if one of the operand is
having x or
z value; the result out is having all bits x i.e. out =
8'bxxxxxxxx.
& while simulating with NC-SIM, the LSB bit comes x only & all
other
bits set to zero. i.e. the result is out = 8'b0000000x.
please tell me which one is true result.

My understanding is that the result of any comparison in
Verilog is 1'b1 (true), 1'b0 (false) or 1'bX (unknown).
If you then assign this self-determined single bit result
to an 8-bit output, then it should be zero-extended in
the same way as any other copy operation in Verilog.
So I suggest that 8'b0000000X is probably correct.

I'd like to hear other opinions (Steven Sharp???) but
otherwise I intend to report this to Mentor as a bug.

As someone else has pointed out, it's strange that you
provide an 8-bit output for what is clearly a 1-bit result.
Did you intend this instead...

assign out = (in0 < in1) ? in1 : in0;

which will give you the larger of the two values?
In this case, a single-bit unknown in one of the inputs
may or may not propagate to the output...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Svilen Krustev]

Jonathan Bromley wrote:

On 10 Oct 2005 06:16:39 -0700, "jitendra" <jitendra.jeet@gmail.com
wrote:


hi all,
if my code is like this:

module mod_greater(out, in0, in1);
input [7:0] in0, in1;
output [7:0] out;
assign out = in0 < in1;
endmodule

now, with simulating with Modelsim if one of the operand is
having x or
z value; the result out is having all bits x i.e. out =
8'bxxxxxxxx.
& while simulating with NC-SIM, the LSB bit comes x only & all
other
bits set to zero. i.e. the result is out = 8'b0000000x.
please tell me which one is true result.


My understanding is that the result of any comparison in
Verilog is 1'b1 (true), 1'b0 (false) or 1'bX (unknown).
If you then assign this self-determined single bit result
to an 8-bit output, then it should be zero-extended in
the same way as any other copy operation in Verilog.
So I suggest that 8'b0000000X is probably correct.

If I remember correctly there was a difference between verilog 95 and

2001 (or system verilog) about filling the unassigned positions - that
seems to be the case here. I don't know the Mentor tool, but it simply
may follow the 95 rules?

I'd like to hear other opinions (Steven Sharp???) but
otherwise I intend to report this to Mentor as a bug.

As someone else has pointed out, it's strange that you
provide an 8-bit output for what is clearly a 1-bit result.
Did you intend this instead...

assign out = (in0 < in1) ? in1 : in0;

which will give you the larger of the two values?
In this case, a single-bit unknown in one of the inputs
may or may not propagate to the output...

 

accroding to verilog standard if any number is signed then only it's
bits are expanded by msb bit of number. relational operators gives
unsigned result so in the example given by jitendra, out should have x
only at lsb, as it should be expanded by zeros. i think this could be a
bug of modelsim.

rajesh

 

As various other posters have said, the correct result is out =
8'b0000000x.

From IEEE Std 1364-2001, Table 29, the bit length of the result of the
'<' operator is 1 bit. From section 4.5.1, comparison results are

unsigned, regardless of the operands. From sections 4.5.2 and 4.5.3,
sign extension is done only if the type is signed.

So when this result is extended from 1 bit to the 8 bit size of the
result, this should be unsigned or zero-extension. That means the
upper 7 bits should come out zero.

The result is the same in Verilog-1995.

This is apparently a bug in Modelsim.