about rejection time

[ramzi]

are there so who can help me. My question is so easy ;-)

If I have an invertor gate ("not")
with this description (in an SDF file for example) :


delay : * 0->1 (rising):
* delay = 8
* r-limit = e-limit = 4 (rejection time)
* 1->0 (falling):
* delay = 6
* r-limit = e-limit = 4

what's the out-put, if the in-put is :
___ ________________
__/ \_/
0 3 4 9

is it this :
___________
\____________
0 8

or this :
_________________
\___________
0 3 4 9 12
(=4+8)


thank you in advance ...

 

[Jim Lewis]

Welcome to the web. Let me do your homework for you.
I think not.

This is a fairly simple problem to code,
why don't you try it.

If the class book is bad, get either J. Bhasker's,
"A VHDL Primer", or Peter Ashenden's, "A designer's
guide to VHDL." Read about signal assignments and
event queuing.

If you don't want to learn the material, don't take
the class - you are wasting your time.

If you are looking for information on VITAL, see
Doug Perry's book titled VHDL (I think third
edition).

Good Luck.
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



ramzi wrote:

are there so who can help me. My question is so easy ;-)

If I have an invertor gate ("not")
with this description (in an SDF file for example) :


delay : * 0->1 (rising):
* delay = 8
* r-limit = e-limit = 4 (rejection time)
* 1->0 (falling):
* delay = 6
* r-limit = e-limit = 4

what's the out-put, if the in-put is :
___ ________________
__/ \_/
0 3 4 9

is it this :
___________
\____________
0 8

or this :
_________________
\___________
0 3 4 9 12
(=4+8)


thank you in advance ...