About RAM

[Okashii]

Hi there, I was reading the XST User Guide
(http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/xst.pdf) and I came
across examples of ram inference with vhdl. May I know whether ram are
usually used for access to shared resources (like arrays in the those
examples), or are there other uses for them?

Also, if I want to read and write shared resources from different processes,
should I be using a bus?

 

[Mike Treseler]

Okashii wrote:

examples of ram inference with vhdl. May I know whether ram are
usually used for access to shared resources (like arrays in the those
examples), or are there other uses for them?

RAM is a collection or registers that
I can't wire to directly. The upside
is that for most devices, a large RAM array
is much more efficient that a large register array.
FPGA block ram is commonly used for hash/trigger tables,
fifos and other data buffers.

Also, if I want to read and write shared resources from different processes,
should I be using a bus?

I like to minimize shared resources.
If they are needed, I wrap a server
entity around them and interface with
synchronous data and ready/ack handshakes.

top entity: [device pins]
|
top signals: handshake_signals port_maps
| | | | |
design entities: [server][client][mixed][direct]


-- Mike Treseler

 

[Andy Peters]

Okashii wrote:

Hi there, I was reading the XST User Guide
(http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/xst.pdf) and I came
across examples of ram inference with vhdl. May I know whether ram are
usually used for access to shared resources (like arrays in the those
examples), or are there other uses for them?

Well, I suppose one could use RAM wherever one needed to store data.

The one downside of RAM, as compared to building registers out of
flip-flops, is that you need to supply an address to read the RAM. In
other words, all data stored in the RAM are not immediately available.
A register output of course is always available.

Also, if I want to read and write shared resources from different processes,
should I be using a bus?

I suppose so ... I can't think of any other mechanism ...

-a

 

[Andy]

Okashii wrote:

Hi there, I was reading the XST User Guide
(http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/xst.pdf) and I came
across examples of ram inference with vhdl. May I know whether ram are
usually used for access to shared resources (like arrays in the those
examples), or are there other uses for them?

Also, if I want to read and write shared resources from different processes,
should I be using a bus?

Here is an excellent article on using ram in fpga logic design:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_perf_time

In case that does not work, search for "Performance + Time = Memory" on
xilinx's website.

Think of it as time division multiplexing multiple channels with the
same combinatorial logic, and using ram instead of flops for all your
storage. A simple counter sequences through the memory addresses so
each channel gets processed, one at a time. I've used this in the past
with excellent results, in regards to both performance and utilization.

Andy