About multiple targets

[smu]

Hello,

Until now, I used especially the ACTEL FPGAs.
Today, I start to use FPGAs of other manufacturers.
It seems that it is possible to define several architectures for an
entity but I did not find the appropriate syntax.
Which is correct syntax to declare several architectures of an entity?
And how selection between these different architectures can be done?

I need this syntax because I want to optimize my design for each target.

Thank you in advance

smu

 

[Mike Treseler]

smu wrote:

It seems that it is possible to define several architectures for an
entity but I did not find the appropriate syntax.

http://groups.google.com/groups?q=vhdl+default+binding+configuration

-- Mike Treseler

 

[Neo]

smu <pas@d.adresse> wrote in message news:<cnvmom$2k9$1@s5.feed.news.oleane.net>...

Hello,

Until now, I used especially the ACTEL FPGAs.
Today, I start to use FPGAs of other manufacturers.
It seems that it is possible to define several architectures for an
entity but I did not find the appropriate syntax.
Which is correct syntax to declare several architectures of an entity?
And how selection between these different architectures can be done?

I need this syntax because I want to optimize my design for each target.

Thank you in advance

smu

The syntax is :
configuration <config_name> of <entity_name> is
for <reqd_architecture_name>
end for;
end configuration <config_name>;

previous to this you should have those architectures defined in the
entity.
by default if you have multiple architectures in an entity I think if
you dont configure, then the last architecture compiled will be taken
for simulation.

-Neo

 

[Ralf Hildebrandt]

smu wrote:

It seems that it is possible to define several architectures for an
entity but I did not find the appropriate syntax.
Which is correct syntax to declare several architectures of an entity?
And how selection between these different architectures can be done?

I need this syntax because I want to optimize my design for each target.

Beside the possibility to select an architecture with the configuration
as Mike an Neo have stated there is another option to achieve
target-specific designs:
You could use generic parameters. With them you could drive
generate-statements as well normal if-then descisions.

The advantage of generics yould be, that you only have to provide one
architecture. This is especially useful, if there are only slight
optimizations for special designs included. Bugfixing during development
is much easier as you don't have to modify many architecture files, if
something has to be changed.
The disadvantage is the bigger source code which makes it harder to
understand.

If you have very different VHDL source for each target - take
configurations, if there are only slight differences - take generic
parameters.

Ralf

 

[jtw]

-snip-

By supposing that we have a FOO entity and three associated architectures
(FOO_ACTEL, FOO_ALTERA and FOO_VHDL), how can we write the code so that we
can choose one of three possibilities?

smu

P.S. I had never used HDL to describe my FPGAs but only schematics.

Generics in your configuration. This works wonders for simulation.

Since the architectures would be in different files, you would select the
appropriate one in your synthesis project file.

JTW

 

[smu]

Neo wrote:

smu <pas@d.adresse> wrote in message news:<cnvmom$2k9$1@s5.feed.news.oleane.net>...

Hello,

Until now, I used especially the ACTEL FPGAs.
Today, I start to use FPGAs of other manufacturers.
It seems that it is possible to define several architectures for an
entity but I did not find the appropriate syntax.
Which is correct syntax to declare several architectures of an entity?
And how selection between these different architectures can be done?

I need this syntax because I want to optimize my design for each target.

Thank you in advance

smu


The syntax is :
configuration <config_name> of <entity_name> is
for <reqd_architecture_name
end for;
end configuration <config_name>;

previous to this you should have those architectures defined in the
entity.
by default if you have multiple architectures in an entity I think if
you dont configure, then the last architecture compiled will be taken
for simulation.

-Neo

By supposing that we have a FOO entity and three associated
architectures (FOO_ACTEL, FOO_ALTERA and FOO_VHDL), how can we write the
code so that we can choose one of three possibilities?

smu

P.S. I had never used HDL to describe my FPGAs but only schematics.

 

[Neo]

smu <pas@d.adresse> wrote in message news:<co2807$pck$1@s5.feed.news.oleane.net>...

Neo wrote:
smu <pas@d.adresse> wrote in message news:<cnvmom$2k9$1@s5.feed.news.oleane.net>...

Hello,

Until now, I used especially the ACTEL FPGAs.
Today, I start to use FPGAs of other manufacturers.
It seems that it is possible to define several architectures for an
entity but I did not find the appropriate syntax.
Which is correct syntax to declare several architectures of an entity?
And how selection between these different architectures can be done?

I need this syntax because I want to optimize my design for each target.

Thank you in advance

smu


The syntax is :
configuration <config_name> of <entity_name> is
for <reqd_architecture_name
end for;
end configuration <config_name>;

previous to this you should have those architectures defined in the
entity.
by default if you have multiple architectures in an entity I think if
you dont configure, then the last architecture compiled will be taken
for simulation.

-Neo

By supposing that we have a FOO entity and three associated
architectures (FOO_ACTEL, FOO_ALTERA and FOO_VHDL), how can we write the
code so that we can choose one of three possibilities?

smu

P.S. I had never used HDL to describe my FPGAs but only schematics.

Now suppose you have all the 3 architectures in a entity FOO then for
choosing a particular architecture say FOO_ALTERA in the same module
you have to write in the end:
configuration one_of_three of FOO is
for FOO_ALTERA
end for;
end configuration one_of_three;

The same format applies with some slight changes when you choose the
architectures in a top level module while instantiating the
components.

 

[rickman]

smu wrote:

Hello,

Until now, I used especially the ACTEL FPGAs.
Today, I start to use FPGAs of other manufacturers.
It seems that it is possible to define several architectures for an
entity but I did not find the appropriate syntax.
Which is correct syntax to declare several architectures of an entity?
And how selection between these different architectures can be done?

I need this syntax because I want to optimize my design for each target.

I can't answer your question, but you might not need completely separate
architectures for each entity. When I need to specify target specific
hardware descriptions, I use GENERATE statements. They work a bit like
#define in C, but can also do loops and conditionals.

I find that I don't need to completely change my code between targets,
just small parts like block rams and such.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
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