about including file in testbench

[snehashis]

dear friends,
I implemented a filter,and i want to give the inputs as serial
inputs(8bit serial input).I have a large number of inputs(2^16)and i have
it written in a file.how can i open the file and read one data at each
clock from it in my testbench?It will be very helpful if exact syntax is
given.I appreciate any help .

 

[info_]

snehashis wrote:

dear friends,
I implemented a filter,and i want to give the inputs as serial
inputs(8bit serial input).I have a large number of inputs(2^16)and i have
it written in a file.how can i open the file and read one data at each
clock from it in my testbench?It will be very helpful if exact syntax is
given.I appreciate any help .


Is it an assignment ?

This information isn't hard to find... and you should
probably make just a small attempt before posting.
I think one learns more with a small effort rather than
by cutting pasting somebody else's code... I hope I'm wrong there.


anyway....

use STD.Textio.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_std.all;
use IEEE.Std_Logic_Textio.all;


then, as an example, the file to RS232 behavioral model :

process
variable L : line;
variable c : character;
begin
ENDF <= FALSE;
RX <= '1'; -- Idle
file_open(F, filename, read_mode);
wait for BITPeriod;
while not ENDFILE(F) loop
readline (F,L);
while L'length /= 0 loop
if L(1)=';' then -- skip comments
exit;
else
read (L,c);
RSdata <= std_logic_vector(to_unsigned(character'pos(c),8));
RX <= '0'; -- Start bit
wait for BITperiod;
for i in 0 to 7 loop
RX <= RSData(i); wait for BITperiod;
end loop;
RX <= '1'; -- Stop bit
wait for BITperiod*2;
end if;
end loop;
end loop;
file_close (f);
wait for (15 * BITperiod);
report "End of File" severity note;
ENDF <= TRUE;
wait;
end process;

If you read an std_logic vector made of a string of 0s and 1s in the ascii file,
then simply use read (L,vector).
Use an ok boolean if you want to detect malformed vector values :

loop
-- test end of file
readline (file,L);
read (L,vector,Ok);
if Ok then
-- apply
wait until Clk='0';
MyInputs <= Vector;
else
-- warn user in transcript
end if;
end loop;

etc...

 

[snehashis]

this code is not very clear to me.I forgot to mention that I am familiar
with xilinx and cadence verilog simulator.I am also somewhat familiar with
modelsim.
I didnot use others' code.In fact the problem is that i ahve to make a
filter which accepts serial 8bit data from an image(.raw).I have to grab
frames from a video and send it to FPGA and write it into another .raw
file.So the .raw image matrix elements are the serial inputs.Hope i am
able to convey my problem clearly.I need some clarification on the code u
have given:are these IEEE libraries standard?how can i include them to my
testbench?
snehashis

 

[info_]

snehashis wrote:

this code is not very clear to me.I forgot to mention that I am familiar
with xilinx and cadence verilog simulator.I am also somewhat familiar with
modelsim.
I didnot use others' code.In fact the problem is that i ahve to make a
filter which accepts serial 8bit data from an image(.raw).I have to grab
frames from a video and send it to FPGA and write it into another .raw
file.So the .raw image matrix elements are the serial inputs.Hope i am
able to convey my problem clearly.I need some clarification on the code u
have given:are these IEEE libraries standard?how can i include them to my
testbench?
snehashis

Oooops !!

Sorry ! My fault indeed. I forgot I was in the Verilog forum...
Verilog 2001 has an even easier answer to your problem.

In Verilog95, you had to use $readmemb (which is okay provided your
text file has the proper format).

Let me know if you want the code in Verilog.
Sorry again.

Bert

 

[info_]

Verilog 95 example of a table in a text file :

// ***************************************************
// Trivial Sine Wave Generator
// ***************************************************
// Bert Cuzeau
//
// --- Sine Table Simulation style :

reg [4:0] Sine [0:31];

initial $readmemh("Sine.hex",Sine);

-- simple Rom model
always @(CptrQ) RSV_T = Sine [CptrQ];

/* Sine.hex file:
10 13 16 18 1B 1C 1E 1F
1F 1F 1E 1C 1B 18 16 13
10 0D 0A 08 05 04 02 01
01 01 02 04 05 08 0A 0D
*/

// ------------------

You can use $readmemb with binary constants, one or several per line,
and @hex_value to go to a specific address.
Comments (Verilog style) are accepted as well as blank lines.

You have to read the whole file first in a properly dimensioned array,
then get the items individualy with an index.

Verilog2001 is definitely better, similar to C wrt reading from files.

VHDL is in-between, more rigid than Vlg2001 wrt to file input,
but definitely better than Vlg95

Hope this helps,

Bert