Guest
I see that the LRM describes the details of how delays ona a signal
ofr x to any other state transitions are selected.
But I wanted to know, is there a way that we can realize them in
hardware and justify the choice of such values.
I am a software guy, working on a compiler for verilog. So I have
great curiosity about how these values are chosen
and how hardware is realized through verilog
ofr x to any other state transitions are selected.
But I wanted to know, is there a way that we can realize them in
hardware and justify the choice of such values.
I am a software guy, working on a compiler for verilog. So I have
great curiosity about how these values are chosen
and how hardware is realized through verilog