About enable signal

[yiannis]

Hi everybody,

I have a project consisted of FSM's and i want to add enable signal. My
FSM's are in the following format...


always@(posedge clk)
begin
state <= next_state;
output<= n_output;
...
...
end

always@ (input1,input2.....)
begin
next_staste <= state;
case ( something)
A:
begin
next_state <= x;
n_output <= y;
end
B:
.....
endcase
end

Where do i have to put the enable signal?

Also, in cases that i want to power off some modules (for power
efficience), can i do this using the enable signal?

Thanks in advance,

Yiannis

 

Put if (enable) to enable flipflops data in. This is typical low power
design for power-compiler gate-clock off when enable is low.

always@(posedge clk)
if(enable)
begin
state <= next_state;
output<= n_output;
...
...
end

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.

 

[Andy Peters]

yiannis wrote:

Hi everybody,

I have a project consisted of FSM's and i want to add enable signal. My
FSM's are in the following format...

(snip)

Where do i have to put the enable signal?

I suppose it depends on what you wish to enable ...

Also, in cases that i want to power off some modules (for power
efficience), can i do this using the enable signal?

If the target architecture supports clock gating, yes.

-a

 

[keyrun]

i think u can just put the enble signal in the second always statemant
.......... and just use if(enable) after begin...........