About eco_net and __ directives

[parag_paul@hotmail.com]

Are there special nets like __eco_nets.

I have a following call
XDCVD \ag_reg_reg[0] (
.CLK (clk),
.D (bp_i[0]),
.SQ
(ag_reg_reg_0__eco_net));


where I have no ag_reg_reg_0__eco_net with me, in this module.

Are there any special directives like that in Verilog

-Parag

 

[Chris F Clark]

"parag_paul@hotmail.com" <parag_paul@hotmail.com> writes:

Are there special nets like __eco_nets.

I have a following call
XDCVD \ag_reg_reg[0] (
.CLK (clk),
.D (bp_i[0]),
.SQ
(ag_reg_reg_0__eco_net));


where I have no ag_reg_reg_0__eco_net with me, in this module.

Are there any special directives like that in Verilog

-Parag

No, but the use of a previously unnamed net (in certain places, like
instantiations and gate-level primitives), implicitly declares it.
After that statement, if you had no ag_reg_reg_0__eco_net before in
your module, you do now, and it is a net that is 1 bit wide. If there
is a `default_nettype directive, you can modify that behavior. This
"hack" is there to deal with "structural" Verilog translations of
netlists. The previous netlist tools (EDIF?) didn't have declarations
and simply using a name declared it. So, the easiest way to translate
them into Veriolg was to give Verilog a similar functionality.

The use of a \identifier suggests to me that this particular piece of
code is the output of some tool. Such tools, commonly take advantage
of that functionality.