About design clocks

[parag_paul@hotmail.com]

Lets look at the following piece of test case.
Here there is a test bench which will call pli routines to updated
signals a,b. Now in the output , we are seeing that the clock will
change after some other event have happened in the 45 th ns. Is it the
duty of the simulator to see to it that there is a design clock and we
need to update it as the first event in a time cycle.Please send me a
mail if it is confusing.

My general question is that,are design clocks to be specillay declared
so, or we will have to wait till clocking blocks in SV come to help
module top(b);
int i;
bit clk;
shortint j;
shortint k;
input bit [3:0] b;
bit [3:0] a;
reg rst;

always_ff @(clk)
i <= j + k;

always_ff @(posedge clk) begin
if(rst == 0)
a <= b;
else
a <= a+1;
end

initial rst <= 0;

initial clk = 0;
always #5 clk = ~clk;

initial #100 $finish;

endmodule:top

 

[Jonathan Bromley]

On Fri, 24 Aug 2007 04:37:18 -0700,
<parag_paul@hotmail.com> wrote:

Is it the
duty of the simulator to see to it that there is a design clock and we
need to update it as the first event in a time cycle.

Absolutely not. It is the duty of the simulator to simulate
timed changes on various signals, according to the code you wrote.
From the simulator's point of view, the clock is just one of
many signals; it gets no special treatment.

My general question is that,are design clocks to be specillay declared

Of course, you need to do specific things with clock signals
(in particular, use them in the @(posedge...) event control
of a clocked always block). By doing those things, you
create behaviour that matches what an electronics engineer
would expect of a clock. There is no concept of "clock" in
Verilog; there are only variables, nets, time and events.

sor we will have to wait till clocking blocks in SV come to help

Clocking blocks can make it easier to express your intent, if
used correctly. It's also rather easy to use them wrongly,
and get unpredictable or unrealistic results.

Just a general comment: Your SystemVerilog-related questions
would probably get useful answers on the SystemVerilog User
Group forum at www.svug.org
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[parag_paul@hotmail.com]

Thanks Jonathan
That would help. The SV related query was well ingrained into the
context. SO I could not resist putting it here. WIll keep that in mind
for future
-Parag