about addition operator

[jiten]

hi,
i've found that + operator doesn't work with std_logic values.
it works only with std_logic_vector.
i've checked if a,b & c are std_logic values than
c <= a + b; gives compile time errors.
why it happens?
cann't we use + operator with single std_logic values.
regards
jitendra.

 

[Neo]

The "+" operator works with std_logic_values but the addtions of two
single bit makes the result a vector. so you've got type mismatch
there. declaring your "c" as std_logic_vector should make it fine.

 

[Neo]

Jiten,
I see that you have been trying to get your vhdl right by posting to
this newsgroup. Thats fine, but, I feel you have got to know about
digital structures out of a good book like say, Mano before you try
describing hardware in HDLs. It dosent help by just learning how to
write vhdl. you need a good understanding of logic before you can apply
it effectively.