Guest
Greetings,
I want to talk about inertial delays and specify blocks in Verilog. According to varilog spec and what Clifford E. Cummings says: "Inertial delay models only propagate signals to an output after the input signals have remained unchanged (been stable) for a time period equal to or greater than the
propagation delay of the model", which is a literal definition of an inertial delay.
Now, imagine you have instantiated an OR-gate primitive with hash-delay of #3. Initially, both inputs (a, b) are 0. Then, for #2 a is 1, then at the same moment a is 0 and b is 1 for additional #1. Afterwards, both inputs are at 0.
Neither of inputs were stable long enough, yet this produces an output of 1..
Then it gets interesting: make a module with 1 OR gate primitive in it, without a delay. Use a specify block to annotate propagation delays from both inputs to the output with delay of 3. What happens if we run our simulation now? It behaves properly. Nothing happens.
My question is: why there is a discrepancy in this behaviour?
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This gets even trickier with XOR gate primitive and a module, which builds XOR out of NAND2 primitives with same specify block and a module, which contains only XOR primitive + specify block. Different simulators will have incosistent behaviour for all of 3 variants
---
Now, with an OR (NOR+NOT), looking at the transistor schematic, you can somewhat speculate, that when one of the inputs goes down, the pull-up circuitry disables (because of two PMOS in series), and pull-down half starts discharging the output node. And then the second input makes "a final push" to discharge the output node completely. But this is over-complicated reasoning, which will break-down, if we annotate modules that are built out of primitives, as the exact circuitry is unknown and we can't apply such logic.
I would greatly appreciate if someone could clarify this mess
Thank you very much.
Best Regards,
Artjom
I want to talk about inertial delays and specify blocks in Verilog. According to varilog spec and what Clifford E. Cummings says: "Inertial delay models only propagate signals to an output after the input signals have remained unchanged (been stable) for a time period equal to or greater than the
propagation delay of the model", which is a literal definition of an inertial delay.
Now, imagine you have instantiated an OR-gate primitive with hash-delay of #3. Initially, both inputs (a, b) are 0. Then, for #2 a is 1, then at the same moment a is 0 and b is 1 for additional #1. Afterwards, both inputs are at 0.
Neither of inputs were stable long enough, yet this produces an output of 1..
Then it gets interesting: make a module with 1 OR gate primitive in it, without a delay. Use a specify block to annotate propagation delays from both inputs to the output with delay of 3. What happens if we run our simulation now? It behaves properly. Nothing happens.
My question is: why there is a discrepancy in this behaviour?
---
This gets even trickier with XOR gate primitive and a module, which builds XOR out of NAND2 primitives with same specify block and a module, which contains only XOR primitive + specify block. Different simulators will have incosistent behaviour for all of 3 variants
---
Now, with an OR (NOR+NOT), looking at the transistor schematic, you can somewhat speculate, that when one of the inputs goes down, the pull-up circuitry disables (because of two PMOS in series), and pull-down half starts discharging the output node. And then the second input makes "a final push" to discharge the output node completely. But this is over-complicated reasoning, which will break-down, if we annotate modules that are built out of primitives, as the exact circuitry is unknown and we can't apply such logic.
I would greatly appreciate if someone could clarify this mess
Thank you very much.
Best Regards,
Artjom