A very strange problem in verilog delay statement !!

[kapil_kaushik]

In verilog, we use '#' for any delay we require.

The general syntax for it is

#value; or #(value/expression); whatever !!

But what does a verilog statement given below mean:

#`bittime #0;
^
|
no semicolon here !!

Here `bitime is just a constant value....but i m puzzled as to
what is the function of #0 after #`bittime and that too when
there is no semicolon between the two !!


Kindly help
Kapil

 

[Swapnajit Mittra]

"kapil_kaushik" <feelkaushik@rediffmail.com> wrote in message news:<b2b6b750995790223aa24159f9b0aef9@localhost.talkaboutprogramming.com>...

In verilog, we use '#' for any delay we require.

The general syntax for it is

#value; or #(value/expression); whatever !!

But what does a verilog statement given below mean:

#`bittime #0;
^
|
no semicolon here !!

Here `bitime is just a constant value....but i m puzzled as to
what is the function of #0 after #`bittime and that too when
there is no semicolon between the two !!


Kindly help
Kapil

Perhaps the following example will help. Note that any statement
can follow a delay statement. This means a delay statement can
occur after a preceding delay statement and so on.

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module test;

reg a;

initial
$monitor($time, ": a = %b", a);

initial
#10 a = 1'b1;

initial
#10 #10 a = 1'b0;

initial
#10 #10 #10 $finish;
endmodule

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

In effect, the delay values get added before the actual assignments
occur.

So the first assignment of a (to 1'b1) occurs at time = 10, the
assignment a = 1'b0 occurs at time 20 and finally the simulation
ends at time = 30. When you run the above, you will see, as you
would expect:

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
0: a = x
10: a = 1
20: a = 0
$finish at simulation time 30
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Hope this helps.
- Swapnajit.

--
Project VeriPage::: http://www.project-veripage.com

 

[kapil_kaushik]

Thanks a lot Swapnajit
I think that would help me get my work done !
Kapil

 

[Steven Sharp]

"kapil_kaushik" <feelkaushik@rediffmail.com> wrote in message news:<b2b6b750995790223aa24159f9b0aef9@localhost.talkaboutprogramming.com>...

Here `bitime is just a constant value....but i m puzzled as to
what is the function of #0 after #`bittime and that too when
there is no semicolon between the two !!

An arbitrary number of delay controls and event controls can be put
in front of a statement, and they will be executed in sequence before
the statement. So you can say

#1 @(a or b) #10 @(posedge c) $display("finally happened");

This will wait 1, then wait for a or b to change, then wait 10,
then wait for a posedge on c, then print. This sort of thing is
not synthesizable, but is legal Verilog.

The #0 may appear useless. However, it is a common (and dangerous)
trick to try to fix race conditions in a design. It causes the
process to wait 0 time units, but causes it to delay until after
the other processes that are currently ready to run.