A very strange problem in verilog delay statement !!

[kapil_kaushik]

In verilog, we use '#' for any delay we require.

The general syntax for it is

#value; or #(value/expression); whatever !!

But what does a verilog statement given below mean:

#`bittime #0;
^
|
no semicolon here !!

Here `bitime is just a constant value....but i m puzzled as to
what is the function of #0 after #`bittime and that too when
there is no semicolon between the two !!


Kindly help
Kapil

 

[kapil_kaushik]

Thanks a lot Swapnajit
I think that would help me get my work done !
Kapil