A very simple question : RAMB

[Oleg]

Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

 

[Tim Hubberstey]

Oleg wrote:

Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

Look in the Xilinx directory:

vhdl/unisim/unisim_VCOM.vhd

not 100% sure of the filename and path but it is the unisim library you
want.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Sean Durkin]

Oleg wrote:

Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18
Look here:

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0027_11.html

There's example instantiations for all Virtex design elements.

cu,
Sean

 

[Oleg]

Sean Durkin <smd@despammed.com> wrote in message news:<2l1j76F7dockU1@uni-berlin.de>...

Oleg wrote:
Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18
Look here:

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0027_11.html

There's example instantiations for all Virtex design elements.

cu,
Sean

Hi,

Thanks very much guys, the toolbox.xilinx is realy helpfull.

 

[Ralfe Cookson]

benkhalh@hotmail.com (Oleg) wrote in message news:<5f8ab9cc.0407061824.330a99b@posting.google.com>...

Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

Read the section in the "Virtex II Platform FPGA User Guide" on "Using
Block SelectRAM Memory". This can be downloaded from the Xilinx web
site.

If you want to do simulations use Coregen to create a component with
all the simulation parameters needed, such as all the various delays.
You can still use this for synthesis as well.

If you don't need to do simulations you can just look at the library
guide on block selectRAM and find the one you want, then create your
own component declaration using exactly the same component name as in
the library and the exact same port names as appear on the block
diagrams, and then instantiate this component. This should synthesize
and place and route just like any other Xilinx library primitive, such
as IBUF, OBUF, BUFG, etc.

One thing to remember if you do this, is that depending on the model,
some signals such as DI[x:0], DIP[x:0], DO[x:0] and DOP[x:0] are
always considered to be busses, even if they are only one bit wide. If
the port is only one bit wide for your particular model, then you must
still declare it as a buss, i.e. as std_logic_vector(0 downto 0). If
you just use std_logic, you will get synthesis errors.

 

[INS122595]

At the ISE

Edit => Language Templates => VHDL => Component Instantiation => Block RAM

If you dont have the ISE download the WebPack from Xilinx site.

Walter.

"Oleg" <benkhalh@hotmail.com> a écrit dans le message de
news:5f8ab9cc.0407061824.330a99b@posting.google.com...

Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

 

[Oleg]

ralfe.cookson@trw.com (Ralfe Cookson) wrote in message news:<6085b684.0407070643.1c86b8c@posting.google.com>...

benkhalh@hotmail.com (Oleg) wrote in message news:<5f8ab9cc.0407061824.330a99b@posting.google.com>...
Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

Read the section in the "Virtex II Platform FPGA User Guide" on "Using
Block SelectRAM Memory". This can be downloaded from the Xilinx web
site.

If you want to do simulations use Coregen to create a component with
all the simulation parameters needed, such as all the various delays.
You can still use this for synthesis as well.

If you don't need to do simulations you can just look at the library
guide on block selectRAM and find the one you want, then create your
own component declaration using exactly the same component name as in
the library and the exact same port names as appear on the block
diagrams, and then instantiate this component. This should synthesize
and place and route just like any other Xilinx library primitive, such
as IBUF, OBUF, BUFG, etc.

One thing to remember if you do this, is that depending on the model,
some signals such as DI[x:0], DIP[x:0], DO[x:0] and DOP[x:0] are
always considered to be busses, even if they are only one bit wide. If
the port is only one bit wide for your particular model, then you must
still declare it as a buss, i.e. as std_logic_vector(0 downto 0). If
you just use std_logic, you will get synthesis errors.

Thnks Ralfe,

I appreciate your answer too and i have a question for you :
suppose i am using RAMB16_S2, its address port is of 13 bits, if I use
only 5 bits of them then Xilinx suggest to connect unused pins to
logic '1'. Now if the input address bus of my VHDL entity is generic
(not fixed to 5 bits) how can i handle this ?? do u have any VHDL
example???

More over, I am designing a VHDL memory entity data word width (8,16
or 32 bits witdh) of wich is generic so i am using RAMB16_S9,
RAMB16_S18 and RAMB16_S36, we know that there adress and data ports
are of differents width. Each time i want to use one of these 3 RAMB i
do :

if data_word = X generate

RAMB16_SX.......
.........
end generate.

My question still the same : how to handle the generic in a sush
situation??

Any help from any one is highly appreciated.

 

[Just an Illusion]

Hi Oleg,

You can perhaps define them via a concatenation

Take an example:

Your memory address bus is size 5, your ram port is size 13.

Take following pseudo code:

use work.ram_definition_pkg.all; -- The package content the constant
definition RAM_ADDR_SIZE=13
....
entity myRAM is
generic (ADDR_SIZE : integer = 5;
...);
....
constant tie_high_ram : std_logic_vector ( RAM_ADDR_SIZE -1 downto 0) :=
(other => '1');
signal addr_bus_int : std_logic_vector ( RAM_ADDR_SIZE -1 downto 0);
....

addr_bus_int <= tie_high_ram (RAM_ADDR_SIZE -1 downto RAM_ADDR_SIZE -
ADDR_SIZE) && addr_bus (ADDR_SIZE -1 downto 0);
....

inst_RAMB16_S2 : RAMB16_S2
port map ( addr => addr_bus_int,
....

Unfortunately this code require that ADDR_SIZE < RAM_ADDR_SIZE.
A generate can be solve this issue for ADDR_SIZE=RAM_ADDR_SIZE, but I
don't know any solution in case of ADDR_SIZE > RAM_ADDR_SIZE.

Bye,
JaI

Oleg wrote:

ralfe.cookson@trw.com (Ralfe Cookson) wrote in message news:<6085b684.0407070643.1c86b8c@posting.google.com>...


benkhalh@hotmail.com (Oleg) wrote in message news:<5f8ab9cc.0407061824.330a99b@posting.google.com>...


Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18


Read the section in the "Virtex II Platform FPGA User Guide" on "Using
Block SelectRAM Memory". This can be downloaded from the Xilinx web
site.

If you want to do simulations use Coregen to create a component with
all the simulation parameters needed, such as all the various delays.
You can still use this for synthesis as well.

If you don't need to do simulations you can just look at the library
guide on block selectRAM and find the one you want, then create your
own component declaration using exactly the same component name as in
the library and the exact same port names as appear on the block
diagrams, and then instantiate this component. This should synthesize
and place and route just like any other Xilinx library primitive, such
as IBUF, OBUF, BUFG, etc.

One thing to remember if you do this, is that depending on the model,
some signals such as DI[x:0], DIP[x:0], DO[x:0] and DOP[x:0] are
always considered to be busses, even if they are only one bit wide. If
the port is only one bit wide for your particular model, then you must
still declare it as a buss, i.e. as std_logic_vector(0 downto 0). If
you just use std_logic, you will get synthesis errors.




Thnks Ralfe,

I appreciate your answer too and i have a question for you :
suppose i am using RAMB16_S2, its address port is of 13 bits, if I use
only 5 bits of them then Xilinx suggest to connect unused pins to
logic '1'. Now if the input address bus of my VHDL entity is generic
(not fixed to 5 bits) how can i handle this ?? do u have any VHDL
example???

More over, I am designing a VHDL memory entity data word width (8,16
or 32 bits witdh) of wich is generic so i am using RAMB16_S9,
RAMB16_S18 and RAMB16_S36, we know that there adress and data ports
are of differents width. Each time i want to use one of these 3 RAMB i
do :

if data_word = X generate

RAMB16_SX.......
.........
end generate.

My question still the same : how to handle the generic in a sush
situation??

Any help from any one is highly appreciated.

 

[Oleg]

"INS122595" <walter@chasque.apc.org> wrote in message news:<10eqppsbm5o01e2@news.supernews.com>...

At the ISE

Edit => Language Templates => VHDL => Component Instantiation => Block RAM

If you dont have the ISE download the WebPack from Xilinx site.

Walter.

"Oleg" <benkhalh@hotmail.com> a écrit dans le message de
news:5f8ab9cc.0407061824.330a99b@posting.google.com...
Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

Hi Ralfe,

I had the same idea like the one yous suggested but i wasnt sure and
when you are note sure you better ask a fellows ;-).... you know, you
never realy use as much address as its available in the RAMB
especially in my case, i never exeed 8 bits adr_bus width. IF
(condition) generate is very usfull to change to RAMB16_Sx to better
suit the data size especialy if the words are standard
(8,16,32,64...bits width).

Thanks a lot Ralfe for your time, i realy appreciated ;-)

 

[Oleg]

Hi Walter, Thank a lot for the truc, its realy funy : the answer is
right under the nose but we never look there ;-)

Thanks a lot Walter.

At the ISE

Edit => Language Templates => VHDL => Component Instantiation => Block RAM

If you dont have the ISE download the WebPack from Xilinx site.

Walter.