A Verilog Parser and Tools - A Wishlist.

[Ben Marshall]

Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will
make programming in Verilog a little easier. It seems to me that every other
language out there has all of these wonderful tools like linters, style checkers,
and optimisers - but no such luck for Verilog. Unless you have tens of thousands
of dollars for a Cadence/Synopsys/Mentor licence and the time to learn their
billion features and set up a work flow.

My question is this - what sorts of tools would people here find useful? My
current wishlist is this:
- Critical path identifier (something which doesn't take 20 minuets to run on
a grid engine)
- A switching probability analysis tool.
- This could even feed into a rough power & energy estimation tool.
- A simple hierarchy visualiser, which you can feed all your project files into
and which will spit out a digested view of the module hierarchy.
- Proper Doxygen support for Verilog. This will be the first thing I try after
the parser is finished.

What would you like to see?

Thanks, Ben

 

[Johann Klammer]

On 05/31/2016 12:50 PM, Ben Marshall wrote:

Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will
make programming in Verilog a little easier. It seems to me that every other
language out there has all of these wonderful tools like linters, style checkers,
and optimisers - but no such luck for Verilog. Unless you have tens of thousands
of dollars for a Cadence/Synopsys/Mentor licence and the time to learn their
billion features and set up a work flow.

My question is this - what sorts of tools would people here find useful? My
current wishlist is this:
- Critical path identifier (something which doesn't take 20 minuets to run on
a grid engine)
- A switching probability analysis tool.
- This could even feed into a rough power & energy estimation tool.
- A simple hierarchy visualiser, which you can feed all your project files into
and which will spit out a digested view of the module hierarchy.
- Proper Doxygen support for Verilog. This will be the first thing I try after
the parser is finished.

What would you like to see?

Thanks, Ben

An indent like thingy(code formatter).
You'd have to keep the comments too, for that to work.

 

[GaborSzakacs]

Ben Marshall wrote:

Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will
make programming in Verilog a little easier. It seems to me that every other
language out there has all of these wonderful tools like linters, style checkers,
and optimisers - but no such luck for Verilog. Unless you have tens of thousands
of dollars for a Cadence/Synopsys/Mentor licence and the time to learn their
billion features and set up a work flow.

My question is this - what sorts of tools would people here find useful? My
current wishlist is this:
- Critical path identifier (something which doesn't take 20 minuets to run on
a grid engine)
- A switching probability analysis tool.
- This could even feed into a rough power & energy estimation tool.
- A simple hierarchy visualiser, which you can feed all your project files into
and which will spit out a digested view of the module hierarchy.
- Proper Doxygen support for Verilog. This will be the first thing I try after
the parser is finished.

What would you like to see?

Thanks, Ben

I'd like to see a pre-processed source that shows me just what will be
compiled after resolving parameters, macros, generate if, etc. This
would make looking through some Xilinx logic cores much easier, since
often the parameters are set several layers of hierarchy above the
file where they're used, and even within a file there are multiple
layers of dependencies on parameters.

I'd also like to see an editor that highlights clock domain crossings,
i.e. signals on the RHS of a clocked always block that didn't originate
on that clock.

--
Gabor

 

Anything from your current wishlist would be awesome.

 

[Ben Marshall]

Ooh I hadn't thought of that. Verilog is odd in how it organises macros and parameters (in the spec at least, if not in use cases), so I can see how it would be useful.

How would you manage the generated code? Just dump it out into a separate directory which you can compare and trace to the original?

 

[Ben Marshall]

On Wednesday, 1 June 2016 22:03:53 UTC+1, gabor wrote:

Ben Marshall wrote:
Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will
make programming in Verilog a little easier. It seems to me that every other
language out there has all of these wonderful tools like linters, style checkers,
and optimisers - but no such luck for Verilog. Unless you have tens of thousands
of dollars for a Cadence/Synopsys/Mentor licence and the time to learn their
billion features and set up a work flow.

My question is this - what sorts of tools would people here find useful? My
current wishlist is this:
- Critical path identifier (something which doesn't take 20 minuets to run on
a grid engine)
- A switching probability analysis tool.
- This could even feed into a rough power & energy estimation tool.
- A simple hierarchy visualiser, which you can feed all your project files into
and which will spit out a digested view of the module hierarchy.
- Proper Doxygen support for Verilog. This will be the first thing I try after
the parser is finished.

What would you like to see?

Thanks, Ben

I'd like to see a pre-processed source that shows me just what will be
compiled after resolving parameters, macros, generate if, etc. This
would make looking through some Xilinx logic cores much easier, since
often the parameters are set several layers of hierarchy above the
file where they're used, and even within a file there are multiple
layers of dependencies on parameters.

I'd also like to see an editor that highlights clock domain crossings,
i.e. signals on the RHS of a clocked always block that didn't originate
on that clock.

--
Gabor

Ooo I hadn't thought of that. That would be very useful indeed for things like register files as well.

How would you handle the generated source? Just dump it out into an adjacent directory?

 

[Ben Marshall]

On Thursday, 2 June 2016 19:28:58 UTC+1, min...@gmail.com wrote:
> Anything from your current wishlist would be awesome.

Glad to hear it! Doxygen will be first I think, that will act as a good stress test for the parser and syntax tree code. Then I can tweak stuff for the other tools.

 

[GaborSzakacs]

Ben Marshall wrote:

On Wednesday, 1 June 2016 22:03:53 UTC+1, gabor wrote:
Ben Marshall wrote:
Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will
make programming in Verilog a little easier. It seems to me that every other
language out there has all of these wonderful tools like linters, style checkers,
and optimisers - but no such luck for Verilog. Unless you have tens of thousands
of dollars for a Cadence/Synopsys/Mentor licence and the time to learn their
billion features and set up a work flow.

My question is this - what sorts of tools would people here find useful? My
current wishlist is this:
- Critical path identifier (something which doesn't take 20 minuets to run on
a grid engine)
- A switching probability analysis tool.
- This could even feed into a rough power & energy estimation tool.
- A simple hierarchy visualiser, which you can feed all your project files into
and which will spit out a digested view of the module hierarchy.
- Proper Doxygen support for Verilog. This will be the first thing I try after
the parser is finished.

What would you like to see?

Thanks, Ben
I'd like to see a pre-processed source that shows me just what will be
compiled after resolving parameters, macros, generate if, etc. This
would make looking through some Xilinx logic cores much easier, since
often the parameters are set several layers of hierarchy above the
file where they're used, and even within a file there are multiple
layers of dependencies on parameters.

I'd also like to see an editor that highlights clock domain crossings,
i.e. signals on the RHS of a clocked always block that didn't originate
on that clock.

--
Gabor

Ooo I hadn't thought of that. That would be very useful indeed for things like register files as well.

How would you handle the generated source? Just dump it out into an adjacent directory?

That's one possibility. If you had an organized project set up like
most front-end tools these days, it would have the full project
hierarchy so it could parse compile-time known values at any level
of the hierarchy. With a smart editor (think of Microsoft Visual
Studio) You could just hover over a parameter or macro where it's
used and get a little pop-up (like a "tool tip") that shows the value.
Otherwise just save the same source with the resolvable values
changed into constants, either in a parallel directory or with a
different file extension. I am sure there are other ways to do it...

--
Gabor

 

[evilkidder@googlemail.com]

Yosys has a pretty decent verilog parser already. Perhaps you could build on that?

https://github.com/cliffordwolf/yosys/tree/master/frontends/verilog

-Andy


On Tuesday, May 31, 2016 at 11:50:53 AM UTC+1, Ben Marshall wrote:

Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will
make programming in Verilog a little easier. It seems to me that every other
language out there has all of these wonderful tools like linters, style checkers,
and optimisers - but no such luck for Verilog. Unless you have tens of thousands
of dollars for a Cadence/Synopsys/Mentor licence and the time to learn their
billion features and set up a work flow.

My question is this - what sorts of tools would people here find useful? My
current wishlist is this:
- Critical path identifier (something which doesn't take 20 minuets to run on
a grid engine)
- A switching probability analysis tool.
- This could even feed into a rough power & energy estimation tool.
- A simple hierarchy visualiser, which you can feed all your project files into
and which will spit out a digested view of the module hierarchy.
- Proper Doxygen support for Verilog. This will be the first thing I try after
the parser is finished.

What would you like to see?

Thanks, Ben

 

[Ben Marshall]

On Thursday, 9 June 2016 19:44:37 UTC+1, evilk...@googlemail.com wrote:

Yosys has a pretty decent verilog parser already. Perhaps you could build on that?

https://github.com/cliffordwolf/yosys/tree/master/frontends/verilog

-Andy


On Tuesday, May 31, 2016 at 11:50:53 AM UTC+1, Ben Marshall wrote:
Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will
make programming in Verilog a little easier. It seems to me that every other
language out there has all of these wonderful tools like linters, style checkers,
and optimisers - but no such luck for Verilog. Unless you have tens of thousands
of dollars for a Cadence/Synopsys/Mentor licence and the time to learn their
billion features and set up a work flow.

My question is this - what sorts of tools would people here find useful? My
current wishlist is this:
- Critical path identifier (something which doesn't take 20 minuets to run on
a grid engine)
- A switching probability analysis tool.
- This could even feed into a rough power & energy estimation tool.
- A simple hierarchy visualiser, which you can feed all your project files into
and which will spit out a digested view of the module hierarchy.
- Proper Doxygen support for Verilog. This will be the first thing I try after
the parser is finished.

What would you like to see?

Thanks, Ben

Hey Andy

I did indeed consider building on several of the existing verilog front-ends for tools like yosys and icarus verilog. I thought Yoysys in particular was a good one for it's conciseness, and have used it as a reference for trickier parts of the grammar.

I've actually started from scratch for a number of reasons, the main one is that the existing parsers are all built with their corresponding tool in mind - so the AST they generate, while perfect for that use, is hard to use for generic applications. There are pros and cons to this for sure, but hopefully the result will be something which is much easier to use and integrate into other tools.

Thanks for the suggestion!
Ben

 

On Tuesday, May 31, 2016 at 3:50:53 AM UTC-7, Ben Marshall wrote:

Hi All

As a pet project, I am currently building a Verilog parser and abstract syntax
tree generator. My plan is to use this as the basis of various tools which will


Thanks, Ben

Ben,

Is this a one man project or do you want to open it up for open source development?


John Eaton

z3qmtr45

with gmail