F
fpgabuilder
Guest
I have the following piece of code. My intention is to initialize a
register as shown. Part of the hierarchy is generated with a generate
block. parallel_tx is an interface instantiated as a bus. I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block. I would appreciate any insight.
integer i, x, y, z;
initial
begin
for (x=0;x<max_x;x+=1)
for(y=0;y<max_y;y+=1)
for(z=0;z<max_z;z+=1)
begin
tb.adc_brd_bfm.adcFpga_loop[x].adc_brd_fpga_inst.adcRx_loop[y].parallel_tx[z]=
i;
i = i+1;
end
end
register as shown. Part of the hierarchy is generated with a generate
block. parallel_tx is an interface instantiated as a bus. I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block. I would appreciate any insight.
integer i, x, y, z;
initial
begin
for (x=0;x<max_x;x+=1)
for(y=0;y<max_y;y+=1)
for(z=0;z<max_z;z+=1)
begin
tb.adc_brd_bfm.adcFpga_loop[x].adc_brd_fpga_inst.adcRx_loop[y].parallel_tx[z]=
i;
i = i+1;
end
end