A variable index into the generate block

[fpgabuilder]

I have the following piece of code. My intention is to initialize a
register as shown. Part of the hierarchy is generated with a generate
block. parallel_tx is an interface instantiated as a bus. I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block. I would appreciate any insight.

integer i, fpgaChip, fpgaAdcIf, adcIf;
initial
begin
for (fpgaChip=0;fpgaChip<NUM_OF_FPGA_CHIPS;fpgaChip+=1)

for(fpgaAdcIf=0;fpgaAdcIf<NUM_OF_ADC_INTERFACES_PER_FPGA_CHIP;fpgaAdcIf
+=1)
for(adcIf=0;adcIf<NUM_OF_ADC_CHANNELS;adcIf+=1) begin

tb.adc_brd_bfm.adcFpga_loop[fpgaChip].adc_brd_fpga_inst.adcRx_loop[fpgaAdcIf].parallel_tx[adcIf]
= i;
i = i+1;
end
end