A variable index into the generate block

[fpgabuilder]

I have the following piece of code. My intention is to initialize a
register as shown. Part of the hierarchy is generated with a generate
block. parallel_tx is an interface instantiated as a bus. I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block. I would appreciate any insight.

integer i, fpgaChip, fpgaAdcIf, adcIf;
initial
begin
for (fpgaChip=0;fpgaChip<NUM_OF_FPGA_CHIPS;fpgaChip+=1)

for(fpgaAdcIf=0;fpgaAdcIf<NUM_OF_ADC_INTERFACES_PER_FPGA_CHIP;fpgaAdcIf
+=1)
for(adcIf=0;adcIf<NUM_OF_ADC_CHANNELS;adcIf+=1) begin

tb.adc_brd_bfm.adcFpga_loop[fpgaChip].adc_brd_fpga_inst.adcRx_loop[fpgaAdcIf].parallel_tx[adcIf]
= i;
i = i+1;
end
end

 

[glen herrmannsfeldt]

fpgabuilder <parekh.sh@gmail.com> wrote:

I have the following piece of code. My intention is to initialize a
register as shown. Part of the hierarchy is generated with a generate
block. parallel_tx is an interface instantiated as a bus. I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block. I would appreciate any insight.

Remember that verilog is a Hardware Description Language.

You are generating multiple instances of some hardware block,
and then trying to index them. In some cases the index might
just be a multiplexer on the outputs of the different instances.
As far as I understand it, verilog wants you to generate your
own multiplexer in that case. If you are trying to change values
in one instance, then the hardware realization is very different.

Think in terms of hardware blocks and verilog makes much more sense.

-- glen

 

[fpgabuilder]

On Mar 15, 6:53 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

fpgabuilder <parekh...@gmail.com> wrote:
I have the following piece of code.  My intention is to initialize a
register as shown. Part of the hierarchy is generated with a generate
block.  parallel_tx is an interface instantiated as a bus.  I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block.  I would appreciate any insight.

Remember that verilog is a Hardware Description Language.

You are generating multiple instances of some hardware block,
and then trying to index them.  In some cases the index might
just be a multiplexer on the outputs of the different instances.
As far as I understand it, verilog wants you to generate your
own multiplexer in that case.  If you are trying to change values
in one instance, then the hardware realization is very different.

Think in terms of hardware blocks and verilog makes much more sense.

-- glen

Thanks Glen. Basically what I am trying to do is to initialize a
register in each of the interface instance with a different value in
my test-bench. In the real system these registers will be initialized
by a processor.

 

[Jonathan Bromley]

On Mon, 15 Mar 2010 17:25:52 -0700 (PDT), fpgabuilder wrote:

...I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block.

That's correct. Using variables as generate-loop indices
is a slippery slope leading to all sorts of nasty
possibilities: continuous drivers that come and go
dynamically as the values of variables change; accesses
to something that doesn't exist (remember that each
pass around a generate...for loop can be differently
parameterized, and therefore the multiple instances
may have completely different structures); ...

It's a very, very nasty can of worms and Verilog has
sensibly decided to keep the lid on it. You simply
can't do that.

Find some way to create an array of signals, with
one signal used by each element of the structure.
Then you can use a variable to index the array.
--
Jonathan Bromley

 

[fpgabuilder]

On Mar 17, 4:20 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Mon, 15 Mar 2010 17:25:52 -0700 (PDT), fpgabuilder wrote:
...I am not
sure why I am not able to use variables to traverse the hierarchy.
Modelsim complaints that I cannot use a variable index into the
generate block.

That's correct.  Using variables as generate-loop indices
is a slippery slope leading to all sorts of nasty
possibilities: continuous drivers that come and go
dynamically as the values of variables change; accesses
to something that doesn't exist (remember that each
pass around a generate...for loop can be differently
parameterized, and therefore the multiple instances
may have completely different structures); ...

It's a very, very nasty can of worms and Verilog has
sensibly decided to keep the lid on it.  You simply
can't do that.

Find some way to create an array of signals, with
one signal used by each element of the structure.
Then you can use a variable to index the array.
--
Jonathan Bromley

Yes! That is exactly what I did and kicked myself for not thinking
about it soon enough. Sometimes, one just needs to stop staring at the
problem and come back to it later.