A syntax question

[Daku]

Maybe this is a very stupid question, as my Verilog is slightly rusty.
What does "aways @*" mean, does it mean that the 'always' block should
respond to any change in any input ?
A little clarification would be very helpful. Thanks in advance.

 

[glen herrmannsfeldt]

Daku <dakupoto@gmail.com> wrote:

Maybe this is a very stupid question, as my Verilog is slightly rusty.
What does "aways @*" mean, does it mean that the 'always' block should
respond to any change in any input ?
A little clarification would be very helpful.

Personally, I usually use continuous assignment (the assign statement)
much of the time, but yes ,as well as I understand it, the
always @* means to evaluate the block when any signal used as
an input within the block changes.

Verilog lets you write much that isn't synthesizable, though.

always @(clk) q <= d

describes a ff that clocks on either edge of the clock.
(Rare, at least, in current logic devices.)

always @( a or b or c ) q <= d

describes a ff that clocks on changes to any of three signals!

-- glen

 

[unfrostedpoptart]

On Friday, January 13, 2012 4:35:57 AM UTC-8, glen herrmannsfeldt wrote:

Daku <daku...@gmail.com> wrote:
Maybe this is a very stupid question, as my Verilog is slightly rusty.
What does "aways @*" mean, does it mean that the 'always' block should
respond to any change in any input ?

Yes. It was added so people wouldn't forget a signal in the sensitivity list and end up with a latch instead of combinatorial logic.

Personally, I usually use continuous assignment (the assign statement)
much of the time, but yes ,as well as I understand it, the
always @* means to evaluate the block when any signal used as
an input within the block changes.

For simple stuff, yes, an assignment is easier, although you can into the nasty inertial vs transport delay behavior of Verilog in some cases.

For big blocks, like the combinatorial part of a state machine with lots in inputs and outputs, you'll want the always block.

In System Verilog, the always @* is now replaced with always_comb (and always_ff for block that infer registers). This has a couple of advantages. First, it tell the simulator and synthesis tools that you really don't want latches or flip-flops. This lets the tool analyze your code and warn you if you put in something that doesn't match this behavior. A lot of the System Verilog keywords are like this in telling the tools what you were trying to do instead of relying on certain templates or pragmas in comments to help the tools.

The other thing, if I remember correctly, is that @* doesn't (or does?) trigger at time zero. Whatever it does is wrong and fixed in always_comb. For most code it doesn't make a difference, but can bite you in certain cases.

David

 

[p56d]

Il 13/01/12 13:35, glen herrmannsfeldt ha scritto:

always @(clk) q<= d

describes a ff that clocks on either edge of the clock.
(Rare, at least, in current logic devices.)

always @( a or b or c ) q<= d

Please let me know, are these synthesizable?

always @(clk) q = d;

always @( a or b or c ) q = d;


Thank you

 

[glen herrmannsfeldt]

p56d <p55d@titintit.it> wrote:

Il 13/01/12 13:35, glen herrmannsfeldt ha scritto:
always @(clk) q<= d

describes a ff that clocks on either edge of the clock.
(Rare, at least, in current logic devices.)

always @( a or b or c ) q<= d

Please let me know, are these synthesizable?

always @(clk) q = d;

always @( a or b or c ) q = d;

Yes, likely not in currently popular logic families.

With the popularity of DDR, clock on both edges, RAM, though,
maybe not so much longer for the former. For the latter, if you
have clock on both edges logic, then

always @( a ^ b ^ c )

should do it. (So why is there an or option?)

-- glen

 

[unfrostedpoptart]

Several years ago I was working on some Xilinx FPGAs that had dual-edged flipflops. I think the syntax was this:

always @ (posedge clk or negedge clk) ...

So it still wanted to see an edge. Otherwise, you're inferring a latch and 99.9999% of the time, you shouldn't be doing that (IBM's lssd architecture is a whole other thing...).

David

 

[Gabor]

unfrostedpoptart wrote:

Several years ago I was working on some Xilinx FPGAs that had dual-edged flipflops. I think the syntax was this:

always @ (posedge clk or negedge clk) ...

So it still wanted to see an edge. Otherwise, you're inferring a latch and 99.9999% of the time, you shouldn't be doing that (IBM's lssd architecture is a whole other thing...).

David

The real answer to what can be synthesized rests in the synthesis tool
you're using. For example, Xilinx allows dual edge flops to be
inferred for some CPLD families, but not for FPGA's.

-- Gabor

 

[Cary R.]

On 1/13/2012 4:35 AM, glen herrmannsfeldt wrote:

Daku<dakupoto@gmail.com> wrote:
Maybe this is a very stupid question, as my Verilog is slightly rusty.
What does "aways @*" mean, does it mean that the 'always' block should
respond to any change in any input ?
A little clarification would be very helpful.

Personally, I usually use continuous assignment (the assign statement)
much of the time, but yes ,as well as I understand it, the
always @* means to evaluate the block when any signal used as
an input within the block changes.

The standard specifies that all nets and variable identifiers in the
body of the @* will be added except for identifiers that only appear in
wait expressions, event expressions or as an L-value hierarchical
variable identifier (the actual L-value variable).

So @* will be sensitive to the index of a L-value variable select. It's
also worth noting that the select operators are not considered when
determining the sensitivity list. This makes @* sensitive to the entire
variable even for a constant select. This is true for both vectors and
arrays (e.g. array[0] will create a sensitivity to the entire array not
just the 0 element of the array).

Cary