A simple verilog simulator

[Kecheng]

Hi

I'm trying to writing a simple verilog RTL simulator, my goal is
simple. I only want to update the states after each clock cycle. For
instance, my simulator will take a verilog file. I run my simulator by
one clock, I calculate all variable's value and simulate next clock,
and then calculate all variable's value. I'm wondering whether there
are some existing tools or experience.

Thanks.

 

[Pinhas]

There is a very good open source verilog simulator at http://www.icarus.com/.
I use it a lot see many examples at
http://bknpk.no-ip.biz/

Kecheng כתב:

Hi

I'm trying to writing a simple verilog RTL simulator, my goal is
simple. I only want to update the states after each clock cycle. For
instance, my simulator will take a verilog file. I run my simulator by
one clock, I calculate all variable's value and simulate next clock,
and then calculate all variable's value. I'm wondering whether there
are some existing tools or experience.

Thanks.

 

[mahesh]

On Jul 7, 2:12 pm, Kecheng <kecheng...@gmail.com> wrote:

Hi

I'm trying to writing a simple verilog RTL simulator, my goal is
simple. I only want to update the states after each clock cycle. For
instance, my simulator will take a verilog file. I run my simulator by
one clock, I calculate all variable's value and simulate next clock,
and then calculate all variable's value. I'm wondering whether there
are some existing tools or experience.

Thanks.

Hi Kechung,

In modelsim simulator u can see the states,variables.......

hesh.

 

[Chris F Clark]

Kecheng <kechenghao@gmail.com> writes:

I'm trying to writing a simple verilog RTL simulator, my goal is
simple. I only want to update the states after each clock cycle.

What you are describing is often called a cycle-based simulator. I
was part of a team that wrote such a beast. You can only do a sbuset
of verilog with it, and somehow you must "identify" the clock(s).
Note it sounds much simpler to write than it is.

Hope this helps,
-Chris

******************************************************************************
Chris Clark Internet: christopher.f.clark@compiler-resources.com
Compiler Resources, Inc. or: compres@world.std.com
23 Bailey Rd Web Site: http://world.std.com/~compres
Berlin, MA 01503 voice: (508) 435-5016
USA fax: (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

On Jul 9, 4:20 pm, Chris F Clark <c...@shell01.TheWorld.com> wrote:

Kecheng <kecheng...@gmail.com> writes:
I'm trying to writing a simple verilog RTL simulator, my goal is
simple. I only want to update the states after each clock cycle.

What you are describing is often called a cycle-based simulator. I
was part of a team that wrote such a beast. You can only do a sbuset
of verilog with it, and somehow you must "identify" the clock(s).
Note it sounds much simpler to write than it is.

Hope this helps,
-Chris

******************************************************************************
Chris Clark Internet: christopher.f.cl...@compiler-resources.com
Compiler Resources, Inc. or: comp...@world.std.com
23 Bailey Rd Web Site:http://world.std.com/~compres
Berlin, MA 01503 voice: (508) 435-5016
USA fax: (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

Simple Verilog Simulator

All in the same sentence - what am I missing?

John Providenza.

 

On Jul 7, 5:12 pm, Kecheng <kecheng...@gmail.com> wrote:

Hi

I'm trying to writing a simple verilog RTL simulator, my goal is
simple. I only want to update the states after each clock cycle. For
instance, my simulator will take a verilog file. I run my simulator by
one clock, I calculate all variable's value and simulate next clock,
and then calculate all variable's value. I'm wondering whether there
are some existing tools or experience.

Thanks.

ftp://metalab.unc.edu/pub/linux/apps/circuits/
File:ver-1.3.37.tgz

look in src/ver and sys/cyco.

Hope this helps,
-Tony