a simple question

[Rafal Pietrak]

..... although, not for me at the moment

I try to write my first sentences in VHDL. Today, it's one with 4-bit
adder and carry propagation (verbatim included at the end of this post).

Only it doesn't synthesize into a 4-bit adder with carry, but into a 5-bit
one instead. The commented-out lines are my attempt to constrain the
synthesizer to 4-bits, but it appears, that I loose carry in the process .

I'd appreciate any hint on 'how to hint' the synthesizer, to GIVE ME THE
CARRY (my apology for the outburst from 4-bit adder (and not expand
the adder, as it does). I'd like this because I plan to put this into a
CPLD with 4-bit granularity, and I'd like to make the job for place&route
as easy as possible .

I'd really appreciate any comment! (including such: "don't do that;
place&route are inteligent beasts - unlike synthesizes, they do an
excelent job and fix easily whatever synthesizer messed up").

-------------------------------------------------
entity test1 is
generic ( MWS : natural := 4;
DataBW : natural := MWS; AddressBW : natural := 2*MWS);
Port ( data : inout std_logic_vector(DataBW-1 downto 0);
addr : out std_logic_vector(AaddressBW-1 downto 0);
clk : in std_logic;
reset : in std_logic);
end test1;

architecture Behavioral of test1 is
signal accu: std_logic_vector(2*MWS-1 downto 0);
alias accu_l: std_logic_vector(MWS-1 downto 0) is accu(MWS-1 downto 0);
alias accu_h: std_logic_vector(MWS-1 downto 0) is accu(2*MWS-1 downto MWS);

begin
process(clk,reset)
variable tmp: std_logic_vector(MWS downto 0);
begin
if (reset = '0') then
accu <= (others => '0');
elsif rising_edge(clk) then
-- tmp := accu_l + data;
tmp := ("0" & accu_l) + data;
accu_l <= tmp;
-- if (tmp(MWS) = '1') then
-- accu_h <= accu_h + 1;
accu_h <= accu_h + tmp(MWS);
-- end if;
end if;
end process;

addr <= accu;

end Behavioral;