A simple question

V

Ved

Guest
Hi all,
Just a simple question, I discussed with many people and got different
analysis.
Just want comments from you guys.

Consider a 2 input NAND gate.
Output is fedback to one input.
Second input is given sequence ---> 0 1 1 1 1.......

What will be output ?

Some say it will be clock havind pulsewidth of propagation delay.

While some say that it will get saturated to a constant 1.

Please give your opinion.

Regards,
Ved
 
Ved wrote:
Hi all,
Just a simple question, I discussed with many people and got different
analysis.
Just want comments from you guys.

Consider a 2 input NAND gate.
Output is fedback to one input.
Second input is given sequence ---> 0 1 1 1 1.......

What will be output ?

Some say it will be clock havind pulsewidth of propagation delay.

While some say that it will get saturated to a constant 1.

Please give your opinion.
Click to expand...
My opinion is that the problem is not answerable given the
above information.

When the second input is 0, the output is clearly, 1.

But when the second input is 1, the other input and output
become an inverter with its output tied back to its input.
And that has two distinct possibilities, depending on the
exact transfer function (gain and phase shift versus
frequency) of that inverter. If the phase shift does not
approach 180 degrees (not counting the initial 180 degrees
caused by inversion) by the frequency where the gain falls
below 1, the output will settle, eventually, to some
intermediate value between 1 and 0 (a stable negative
feedback controlled bias situation).

But if, at the frequency where the gain falls to 1, if the
additional phase shift is 180 degrees or more, the output
will oscillate in some wave shape between a sine wave and a
square wave. The exact wave depends on the exact gain and
phase frequency response curves.

Simple questions often do not have simple answers.
Such is life.
 
"Ved" <vedpsingh@gmail.com> wrote in message
news:abf53904-2433-4ccb-b975-def3d3a875c7@s36g2000prg.googlegroups.com...
Hi all,
Just a simple question, I discussed with many people and got different
analysis.
Just want comments from you guys.

Consider a 2 input NAND gate.
Output is fedback to one input.
Second input is given sequence ---> 0 1 1 1 1.......

What will be output ?

Some say it will be clock havind pulsewidth of propagation delay.

While some say that it will get saturated to a constant 1.

Please give your opinion.

Regards,
Ved
Click to expand...
With a NAND gate both inputs must be '1' to get an O/P '0' so either input
at '0' will force O/P '1', feeding the O/P back to one of the inputs while
the other is held high will very likely force it into its linear range.
 
On Nov 18, 9:41 am, John Popelish <jpopel...@rica.net> wrote:
Ved wrote:
Hi all,
Just a simple question, I discussed with many people and got different
analysis.
Just want comments from you guys.

Consider a 2 input NAND gate.
Output is fedback to one input.
Second input is given sequence ---> 0 1 1 1 1.......

What will be output ?

Some say it will be clock havind pulsewidth of propagation delay.

While some say that it will get saturated to a constant 1.

Please give your opinion.

My opinion is that the problem is not answerable given the
above information.

When the second input is 0, the output is clearly, 1.

But when the second input is 1, the other input and output
become an inverter with its output tied back to its input.
And that has two distinct possibilities, depending on the
exact transfer function (gain and phase shift versus
frequency) of that inverter. If the phase shift does not
approach 180 degrees (not counting the initial 180 degrees
caused by inversion) by the frequency where the gain falls
below 1, the output will settle, eventually, to some
intermediate value between 1 and 0 (a stable negative
feedback controlled bias situation).

But if, at the frequency where the gain falls to 1, if the
additional phase shift is 180 degrees or more, the output
will oscillate in some wave shape between a sine wave and a
square wave. The exact wave depends on the exact gain and
phase frequency response curves.

Simple questions often do not have simple answers.
Such is life.
Click to expand...
Adding a delay into that 'feedback' made a real nice 'gated
oscillator' in a project I was part of some years ago. Count the
pulses to turn the oscillator off after a specific count. It was a
line rate blanking / DC restore subsystem of a film to video scanner
that worked regardless of the sweep rate.

GG
 
ian field wrote:

With a NAND gate both inputs must be '1' to get an O/P '0' so either input
at '0' will force O/P '1', feeding the O/P back to one of the inputs while
the other is held high will very likely force it into its linear range.
Click to expand...
Try it with a triple buffered CMOS gate.
 
On Sun, 18 Nov 2007 18:16:54 GMT, "ian field" <dai.ode@ntlworld.com>
wrote:

"Ved" <vedpsingh@gmail.com> wrote in message
news:abf53904-2433-4ccb-b975-def3d3a875c7@s36g2000prg.googlegroups.com...
Hi all,
Just a simple question, I discussed with many people and got different
analysis.
Just want comments from you guys.

Consider a 2 input NAND gate.
Output is fedback to one input.
Second input is given sequence ---> 0 1 1 1 1.......

What will be output ?

Some say it will be clock havind pulsewidth of propagation delay.

While some say that it will get saturated to a constant 1.

Please give your opinion.

Regards,
Ved

With a NAND gate both inputs must be '1' to get an O/P '0' so either input
at '0' will force O/P '1', feeding the O/P back to one of the inputs while
the other is held high will very likely force it into its linear range.
Click to expand...
Classic TTL and ECL would do that. Most cmos parts, with multiple lag
stages and tons of gain, will oscillate.

John
 
"Ved" <vedpsingh@gmail.com> wrote in message
news:abf53904-2433-4ccb-b975-def3d3a875c7@s36g2000prg.googlegroups.com...
Hi all,
Just a simple question, I discussed with many people and got different
analysis.
Just want comments from you guys.

Consider a 2 input NAND gate.
Output is fedback to one input.
Second input is given sequence ---> 0 1 1 1 1.......

What will be output ?

Some say it will be clock havind pulsewidth of propagation delay.

While some say that it will get saturated to a constant 1.

Please give your opinion.

Regards,
Ved
Click to expand...
The purely "mathematical" answer is that it will oscillate.

& ~&
1: 0 x -> 0 => x = 1
0 1 -> 0 => x = 1
2: 1 1 -> 1 => x = 0
1 0 -> 0 => x = 1
3: 1 1 -> 1 => x = 0
....

It will oscillate and the propagation delay determines the pulsewidth.

In really, I suppose, if the delay is very short then it might not oscillate
at all because of capacitance. Either that or it will average out to about
1/2 the voltage which will either settle into some limit or be unstable.
 
Ved wrote:

Hi all,
Just a simple question, I discussed with many people and got different
analysis.
Just want comments from you guys.

Consider a 2 input NAND gate.
Output is fedback to one input.
Second input is given sequence ---> 0 1 1 1 1.......

What will be output ?

Some say it will be clock havind pulsewidth of propagation delay.

While some say that it will get saturated to a constant 1.

Please give your opinion.

Regards,
Ved
Normally what will happen in most cases, the output should settle at
Click to expand...
some mid point. It may even oscillate a bit if there is any hysteresis
with some internal capacitance in the right place.
These factors are usually what you call undefined and really isn't a
good idea to build on.

Just my opinion..


--
"I'm never wrong, once i thought i was, but was mistaken"
Real Programmers Do things like this.
http://webpages.charter.net/jamie_5
 
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