a simple addition "+" operator question

[Carson]

Hi,

I have the following code, which can compile without problem in
modelsim (vcom) but when i use vsim, it fails.
------------------------------------
port (
...
x : in std_logic_vector(7 downto 0);
....
);

architecture ...

signal a :std_logic_vector(10 downto 0);
begin
a <= x&"00" + x&"00";
end
-------------------------------------------
when i vcom it, it's okay, but when i run it in modelsim, it said...

# ** Fatal: (vsim-3420) Array lengths do not match. Left is (10 downto
0). Right is (0 to 11).
# Time: 0 ns Iteration: 0 Process: ...
--------------------------------------------
it's very strange, if I do a <= x&"000". It is okay.
but when i use a <= x&"00" + x&"00". it is not...
I can't understand, as i think both are equivalent....

carson

 

[Peter]

"a <= x&"00" + x&"00". it is not..."

Addition of two 10-bit vectors creates a 10-bit result, not 11.
The carry is not taken care of automatically.

/Peter

 

[Peter]

"a <= x&"00" + x&"00". it is not..."

Addition of two 10-bit vectors creates a 10-bit result, not 11.
The carry is not taken care of automatically.

/Peter

 

[Jim Lewis]

Carson,

You need parentheses:
a <= x&"00" + (x&"00");

"&" and "+" have equal precedence and with
left to right evaluation your equation is seen as:
a <= ((x&"00") + x) &"00";

Also the result will be 10 bits and not 11, so if you
want the carry, you must do another concatenation on the
left with 0 (for unsigned) and x(7) for signed.

Cheers,
Jim

Hi,

I have the following code, which can compile without problem in
modelsim (vcom) but when i use vsim, it fails.
------------------------------------
port (
...
x : in std_logic_vector(7 downto 0);
...
);

architecture ...

signal a :std_logic_vector(10 downto 0);
begin
a <= x&"00" + x&"00";
end
-------------------------------------------
when i vcom it, it's okay, but when i run it in modelsim, it said...

# ** Fatal: (vsim-3420) Array lengths do not match. Left is (10 downto
0). Right is (0 to 11).
# Time: 0 ns Iteration: 0 Process: ...
--------------------------------------------
it's very strange, if I do a <= x&"000". It is okay.
but when i use a <= x&"00" + x&"00". it is not...
I can't understand, as i think both are equivalent....

carson

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Colin Marquardt]

Jim Lewis <Jim@SynthWorks.com> writes:

port (
...
x : in std_logic_vector(7 downto 0);
...
);
architecture ...
signal a :std_logic_vector(10 downto 0);
begin
a <= x&"00" + x&"00";
end

Also the result will be 10 bits and not 11, so if you
want the carry, you must do another concatenation on the
left with 0 (for unsigned) and x(7) for signed.

And the style police recommends converting to unsigned/signed and
using resize() to do the extension automatically.

Cheers,
Colin

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