A
Amir
Guest
Hi,
is there a way where I can in do in Verilog such in the following
psuedo-code example?:
task hello;
input a;
input b;
if (be "not-defined")
then random(b);
...
endtask
thanks
-Amir
is there a way where I can in do in Verilog such in the following
psuedo-code example?:
task hello;
input a;
input b;
if (be "not-defined")
then random(b);
...
endtask
thanks
-Amir