H
Hrh
Guest
Greetings all,
I have a question about VLSI test equipment systems. Have you guys
ever experienced bit-flips in the test data stream from head of tester
to circuit under test? What is the typical rate for this situation? Say
I am applying 1Gb of test data to a SoC core, what is the chance to have
1 bit flipped? Even if it is very small (say 10E-6 per bit) I still need
to know it.
What factors can worsen this bit flips if they do exist?
Any help is very much welcome.
Thanks
Sincerely,
HrH
I have a question about VLSI test equipment systems. Have you guys
ever experienced bit-flips in the test data stream from head of tester
to circuit under test? What is the typical rate for this situation? Say
I am applying 1Gb of test data to a SoC core, what is the chance to have
1 bit flipped? Even if it is very small (say 10E-6 per bit) I still need
to know it.
What factors can worsen this bit flips if they do exist?
Any help is very much welcome.
Thanks
Sincerely,
HrH