A question on returned size of a Verilog function

[OutputLogic]

I've the following code:

localparam MY_PARAM = my_function(p1,p2...);

function [5:0] my_function;
...

Sometimes the function returns 7-bit value (a bug).
I'm running synthesis and simulation of that code with two commercial
synthesis tools and two simulators (remain unnamed),
and get three different results:

1. synthesis error
2. warning: size mismatch
3. nothing: synthesizes and simulates correctly, the result is
silently converted to 32-bit


Which one is correct, or it's a gray area in the Verilog spec.


Thanks,
Evgeni

 

[Muzaffer Kal]

On Wed, 12 May 2010 09:47:36 -0700 (PDT), OutputLogic
<evgenist@gmail.com> wrote:

I've the following code:

localparam MY_PARAM = my_function(p1,p2...);

function [5:0] my_function;
...

Sometimes the function returns 7-bit value (a bug).
I'm running synthesis and simulation of that code with two commercial
synthesis tools and two simulators (remain unnamed),
and get three different results:

1. synthesis error
2. warning: size mismatch
3. nothing: synthesizes and simulates correctly, the result is
silently converted to 32-bit


Which one is correct, or it's a gray area in the Verilog spec.

My copy of the 1364-2001 says this about functions: "The function
definition shall implicitly declare a variable, internal to the
function, with the same name as the function. This variable either
defaults to a 1-bit reg or is the same type as the type specified in
the function declaration." In your case there is an implicit 6 bit reg
in your function.
Assuming by "Sometimes the function returns 7-bit value" you mean that
you assign a 7 bit value to the name of the function inside the
function, that value would be truncated on the left to fit in 6 bits
and returned as 6 bits; which makes me think that behavior 2 is the
right one.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

On May 12, 12:47 pm, OutputLogic <evgen...@gmail.com> wrote:

I've the following code:

    localparam MY_PARAM = my_function(p1,p2...);

    function [5:0] my_function;
    ...

Sometimes the function returns 7-bit value (a bug).
I'm running synthesis and simulation of that code with two commercial
synthesis tools and two simulators (remain unnamed),
and get three different results:

  1. synthesis error
  2. warning: size mismatch
  3. nothing: synthesizes and simulates correctly, the result is
silently converted to 32-bit

Which one is correct, or it's a gray area in the Verilog spec.

The size of the function return value is 6 bits. And since there is
no size/type specified on the localparam declaration, it should take
its size from the size of the expression, which is 6 bits. I don't
see any gray area here.