a question in SystemVerilog

[Amir]

Hi,
I'm writing a verification envir in SV, the envir contains 4 masters,
(same module with 4 instantiation) and one slave, since the masters
have the same interface, I created one interface, but I should use a
parameter to define which interface is which, I mean a generic
interface to all 4 masters.

interface mstr_if;

logic [63:0] a_r_addr_<i>;
logic [1:0] a_r_burst_<i>;
logic [3:0] a_r_id_<i>;
logic [3:0] a_r_len_<i>;
logic [2:0] a_r_size_<i>;

endinterface : mstr_if

so when I initialize the interface in the top level , I define the <i>
for each master

mstr_if bus0 #(0);
mstr_if bus0 #(1);
mstr_if bus0 #(2);
mstr_if bus0 #(3);

do you have any idea how can I do in SV?!
thanks in advance

-Amir

 

[Enchanter]

On Dec 22, 10:45 pm, Amir &lt;sting...@gmail.com&gt; wrote:

Hi,
I'm writing a verification envir in SV, the envir contains 4 masters,
(same module with 4 instantiation) and one slave, since the masters
have the same interface, I created one interface, but I should use a
parameter to define which interface is which, I mean a generic
interface to all 4 masters.

interface mstr_if;

logic [63:0] a_r_addr_<i>;
logic [1:0] a_r_burst_<i>;
logic [3:0] a_r_id_<i>;
logic [3:0] a_r_len_<i>;
logic [2:0] a_r_size_<i>;

endinterface : mstr_if

so when I initialize the interface in the top level , I define the &lt;i
for each master

mstr_if bus0 #(0);
mstr_if bus0 #(1);
mstr_if bus0 #(2);
mstr_if bus0 #(3);

do you have any idea how can I do in SV?!
thanks in advance

-Amir

Didn't your master modules connect to the same bus?

 

[Amir]

On Dec 22, 5:30 pm, Enchanter &lt;ensoul.magaz...@gmail.com&gt; wrote:

On Dec 22, 10:45 pm, Amir &lt;sting...@gmail.com&gt; wrote:



Hi,
I'm writing a verification envir in SV, the envir contains 4 masters,
(same module with 4 instantiation) and one slave, since the masters
have the same interface, I created one interface, but I should use a
parameter to define which interface is which, I mean a generic
interface to all 4 masters.

interface mstr_if;

logic [63:0] a_r_addr_<i>;
logic [1:0] a_r_burst_<i>;
logic [3:0] a_r_id_<i>;
logic [3:0] a_r_len_<i>;
logic [2:0] a_r_size_<i>;

endinterface : mstr_if

so when I initialize the interface in the top level , I define the &lt;i
for each master

mstr_if bus0 #(0);
mstr_if bus0 #(1);
mstr_if bus0 #(2);
mstr_if bus0 #(3);

do you have any idea how can I do in SV?!
thanks in advance

-Amir

Didn't your master modules connect to the same bus?

yes sorry , I wrote it wrong in the example
I ment
mstr_if bus0 #(0);
mstr_if bus1 #(1);
mstr_if bus2 #(2);
mstr_if bus3 #(3);

thanks
-Amir

 

On Dec 22, 10:57 am, Amir &lt;sting...@gmail.com&gt; wrote:

Hi,
I'm writing a verification envir in SV, the envir contains 4 masters,
(same module with 4 instantiation) and one slave, since the masters
have the same interface, I created one interface, but I should use a
parameter to define which interface is which, I mean a generic
interface to all 4 masters.

interface mstr_if;

 logic [63:0] a_r_addr_<i>;
 logic [1:0] a_r_burst_<i>;
 logic [3:0] a_r_id_<i>;
 logic [3:0] a_r_len_<i>;
 logic [2:0] a_r_size_<i>;

endinterface : mstr_if

so when I initialize the interface in the top level , I define the &lt;i
for each master

mstr_if bus0 #(0);
mstr_if bus0 #(1);
mstr_if bus0 #(2);
mstr_if bus0 #(3);

While interface use-models are not my area of expertise, I think you
are confused about what the interface is. I assume you have multiple
masters and slaves connected to a single bus. The interface is not a
master or slave connected to a bus. The interface is the bus, and you
connect it to each of the the master and slave modules through an
interface port. The interface may contain code in the form of tasks
and functions that the master and slave modules use to access the bus,
and modports that define a different set of connections to the bus for
masters and slaves, but the interface itself is not a master or slave.

yes sorry , I wrote it wrong in the example
I ment
mstr_if bus0 #(0);
mstr_if bus1 #(1);
mstr_if bus2 #(2);
mstr_if bus3 #(3);

In this case you are declaring 4 different buses. And you don't need
parameterized names to distinguish the same signal in the different
buses. The interface instance does that. The signal bus0.a_r_addr is
distinct from bus1.a_r_addr.