A question from a verilog newbie.

[Jim Huang]

What is the difference between

assign c = a & b;

and

always@( a or b)
begin
c = a & b;
end

 

[John_H]

In the first case, c is a wire. In the second case, c is a reg. Otherwise,
there should be no difference.

"Jim Huang" <jinxu.huang@gmail.com> wrote in message
news:d465dm$cpu$1@plaza.suomi.net...

What is the difference between

assign c = a & b;

and

always@( a or b)
begin
c = a & b;
end

 

[Chris F Clark]

I have recently begun implementing features from the 2001 version of
Verilog in an in-house simulator. In the process I cam across some
surprising parts of the grammar. Now, this may be in part, because I
am working from a draft copy of the standard (as that's what I
currently have a PDF of). However, it's also not in a part of the
standard I would expect to be controversial, so it could also be a
minor oversight.

The productions in question read (with some of the irrelevant
alternatives skipped):

module_declaration ::=
{ attribute_instance } module_keyword module_identifier [ module_parameter_port_list ]
[ list_of_ports ] ; { module_item }
endmodule

module_parameter_port_list ::= # ( parameter_declaration { , parameter_declaration } )

parameter_declaration ::=
parameter [ signed ] [ range ] list_of_param_assignments ;

Now, as I read these rules, it would suggest that one uses both
semcolons and commas to separate parameter declarations that are done
in the module declaration line, like follows:

module mymod #(parameter one = 1;, parameter two = 2, three = 3

My assumption, is that the desired syntax is really without the
semicolons as in:

module_parameter_port_list ::= # ( parameter_declaration_nosemi { , parameter_declaration_nosemi } )

parameter_declaration_nosemi ::=
parameter [ signed ] [ range ] list_of_param_assignments

module mymod #(parameter one = 1, parameter two = 2, three = 3)


Of course, that syntax brings up another slight issue. The grammar is
now LR(2) not LR(1). However, that same problem already exists in the
new "prototype-like" port declarations, so it isn't a bigger challenge
(and I can get my parser generator to handle it, so I don't really
care).


However, I would like confirmation as to what other 2001 tools
support. If other tools support the semicolon free dialect, then I
will support it, as I think it is what the user expects. And I'd be
curious if anyone supports the literal interpretation of the rules
that I've read (or if they have gotten changed and I should tell my
empolyer to buy me a new copy of the standard, which I will probably
do anyway.) I can easily support both dialects (and I think even the
semicolon rather than comma version, although supporting all 3
simultaneously may be a bit of a challenge).

Semicolon rather than comma version:
module_parameter_port_list ::= # ( parameter_declaration { parameter_declaration } )

module mymod #(parameter one = 1; parameter two = 2, three = 3

Thanks for any insight,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

This was reported as an erratum. It has been fixed in the draft for
the 2005 standard. The semicolon has been removed from the production
for parameter_declaration, and a semicolon inserted explicitly after
the uses of it in places other than the ANSI-style port list. So the
official answer matches your "no semicolon" assumption.

NC-Verilog also supports the dialect in your "semicolon rather than
comma" version. It does not support the version with the semicolon
immediately followed by the comma (i.e. the incorrect syntax in the
published grammar).